| Message ID | 20240629-camss_first_post_linux_next-v1-4-bc798edabc3a@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | media: qcom: camss: Add sc7280 support | expand |
On 28/06/2024 19:32, Vikram Sharma wrote: > Enable IMX577 camera sensor for qcs6490-rb3gen2. > > Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 67 ++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index c4cde4328e3d..237231600dca 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts I believe the rb3gen2 can be sold with and without the camera mezzanine [1], so the approach we have taken for a similar situation on rb5 was to have a separate mezzanine dts which includes the baseboard and extends it. arch/arm64/boot/dts/qcom/qrb5165-rb5.dts arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dts Please replicate that model here. [1] https://www.thundercomm.com/product/qualcomm-rb3-gen-2/#versions > @@ -513,6 +513,73 @@ vreg_bob_3p296: bob { > }; > }; > > +&camcc { > + status = "okay"; > +}; > + > +&camss { > + status = "disabled"; once you move this into its own dts the camera should be enabled by default for that .dtb > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* The port index denotes CSIPHY id i.e. csiphy2 */ > + port@3 { > + reg = <3>; copy/past splat from the rb5 port@3 means csiphy3 > + csiphy3_ep: endpoint { > + clock-lanes = <7>; > + data-lanes = <0 1 2 3>; > + remote-endpoint = <&imx412_ep>; > + }; > + }; > + }; > +}; > + > +&cci0 { > + status = "okay"; > +}; You're enabling cci0 here but not the sensor for it - presumably a monochrome sensor attached to one of the other CSIPHYs. Zap cci0 here until you add that other sensor. > + > +&cci1 { > + status = "okay"; > +}; > + > +&cci1_i2c1 { > + camera@1a { > + /* > + * rb3gen2 ships with an imx577. qcom treats imx412 > + * and imx577 the same way. Absent better data do the same here. > + */ > + compatible = "sony,imx412"; > + reg = <0x1a>; The commit log says imx577 but the comapt string says imx412. Choose which one and maintain the namespace. Its an imx577 right ? Upstream kernel has the relevant compat string Commit: 1251663220d9 ("media: i2c: imx412: Add new compatible strings") You can just cherry-pick that commit to your kernel and then the upstream dts and downstream dts will be compatible. > + > + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default", "suspend"; > + pinctrl-0 = <&cam2_default>; > + pinctrl-1 = <&cam2_suspend>; > + > + clocks = <&camcc CAM_CC_MCLK3_CLK>, > + <&camcc CAM_CC_MCLK2_CLK>; > + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>, > + <&camcc CAM_CC_MCLK2_CLK>; This looks funny - why do you have MCLK2 ? One final thing, you appear to be missing some power rails here no ? e.g. rb5 vdda-phy-supply = <&vreg_l5a_0p88>; vdda-pll-supply = <&vreg_l9a_1p2>; --- bod
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index c4cde4328e3d..237231600dca 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -513,6 +513,73 @@ vreg_bob_3p296: bob { }; }; +&camcc { + status = "okay"; +}; + +&camss { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* The port index denotes CSIPHY id i.e. csiphy2 */ + port@3 { + reg = <3>; + csiphy3_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx412_ep>; + }; + }; + }; +}; + +&cci0 { + status = "okay"; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@1a { + /* + * rb3gen2 ships with an imx577. qcom treats imx412 + * and imx577 the same way. Absent better data do the same here. + */ + compatible = "sony,imx412"; + reg = <0x1a>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&cam2_default>; + pinctrl-1 = <&cam2_suspend>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>, + <&camcc CAM_CC_MCLK2_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>, + <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <24000000>, + <24000000>; + + dovdd-supply = <&vreg_l18b_1p8>; + /* avdd-supply = <&vdc_5v>; + * dvdd-supply = <&vdc_5v>; + */ + + port { + imx412_ep: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + &gcc { protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, <GCC_MSS_CFG_AHB_CLK>,