| Message ID | 20240701121355.262259-5-kanakshilledar@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/3] dt-bindings: spi: snps,dw-apb-ssi.yaml: update compatible property | expand |
Kanak, Drew, On Mon, Jul 01, 2024 at 05:43:54PM +0530, Kanak Shilledar wrote: > created spi0 node with fixed clock. the spi0 node > uses synopsis designware driver and has the following > compatible "snps,dw-apb-ssi". the spi0 node is connected > to a SPI NOR flash pad which is left unpopulated on the back > side of the board. > > Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com> > --- > Changes in v2: > - Separated from a single patch file > --- > .../boot/dts/thead/th1520-beaglev-ahead.dts | 9 +++++++++ > .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > .../riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 5 +++++ Didn't you say there was a flash on one of these two boards? > arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++ > 4 files changed, 34 insertions(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > index d9b4de9e4757..3103b74e0288 100644 > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > @@ -17,6 +17,7 @@ aliases { > gpio1 = &gpio1; > gpio2 = &gpio2; > gpio3 = &gpio3; > + spi0 = &spi0; "spi" would sort after "serial". > serial0 = &uart0; > serial1 = &uart1; > serial2 = &uart2; > @@ -52,6 +53,10 @@ &sdhci_clk { > clock-frequency = <198000000>; > }; > > +&spi_clk { > + clock-frequency = <396000000>; > +}; I'm pretty sceptical about adding more of these fixed clocks, rather than waiting for the clock driver. Drew, what do you think? Should we just add one more to your fixup list or would you rather delay? Guess it depends on how long more you think that clock driver is likely to take. Thanks, Conor. > + > &uart_sclk { > clock-frequency = <100000000>; > }; > @@ -79,3 +84,7 @@ &sdio0 { > &uart0 { > status = "okay"; > }; > + > +&spi0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > index 1365d3a512a3..6939bd36560c 100644 > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > @@ -33,6 +33,10 @@ &sdhci_clk { > clock-frequency = <198000000>; > }; > > +&spi_clk { > + clock-frequency = <396000000>; > +}; > + > &uart_sclk { > clock-frequency = <100000000>; > }; > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > index 9a3884a73e13..14b06dd81a9a 100644 > --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > @@ -14,6 +14,7 @@ aliases { > gpio1 = &gpio1; > gpio2 = &gpio2; > gpio3 = &gpio3; > + spi0 = &spi0; > serial0 = &uart0; > serial1 = &uart1; > serial2 = &uart2; > @@ -30,3 +31,7 @@ chosen { > &uart0 { > status = "okay"; > }; > + > +&spi0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > index d2fa25839012..f962de663e7e 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -140,6 +140,12 @@ apb_clk: apb-clk-clock { > #clock-cells = <0>; > }; > > + spi_clk: spi-clock { > + compatible = "fixed-clock"; > + clock-output-names = "spi_clk"; > + #clock-cells = <0>; > + }; > + > uart_sclk: uart-sclk-clock { > compatible = "fixed-clock"; > clock-output-names = "uart_sclk"; > @@ -183,6 +189,16 @@ clint: timer@ffdc000000 { > <&cpu3_intc 3>, <&cpu3_intc 7>; > }; > > + spi0: spi@ffe700c000 { > + compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; > + reg = <0xff 0xe700c000 0x0 0x1000>; > + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&spi_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > uart0: serial@ffe7014000 { > compatible = "snps,dw-apb-uart"; > reg = <0xff 0xe7014000 0x0 0x100>; > -- > 2.45.2 >
On Thu, Jul 04, 2024 at 11:12:43AM +0530, Kanak Shilledar wrote: > Hi > > On Wed, Jul 3, 2024 at 8:15 PM Conor Dooley <conor@kernel.org> wrote: > > > > Kanak, Drew, > > > > On Mon, Jul 01, 2024 at 05:43:54PM +0530, Kanak Shilledar wrote: > > > created spi0 node with fixed clock. the spi0 node > > > uses synopsis designware driver and has the following > > > compatible "snps,dw-apb-ssi". the spi0 node is connected > > > to a SPI NOR flash pad which is left unpopulated on the back > > > side of the board. > > > > > > Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com> > > > --- > > > Changes in v2: > > > - Separated from a single patch file > > > --- > > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 9 +++++++++ > > > .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > > .../riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 5 +++++ > > > > Didn't you say there was a flash on one of these two boards? > Yes, there is a SPI nor flash pad left unpopulated on the bottom side > of the LicheePi 4a > carrier board. https://wiki.sipeed.com/hardware/en/lichee/th1520/lpi4a/2_unbox.html#Board-hardware-overview > notice the reserved pad in the bottom part of the image. Ah right, unpopulated. That makes sense, thanks.
On Thu, Jul 04, 2024 at 09:59:20AM -0700, Drew Fustini wrote: > On Wed, Jul 03, 2024 at 03:45:37PM +0100, Conor Dooley wrote: > > Kanak, Drew, > > > > On Mon, Jul 01, 2024 at 05:43:54PM +0530, Kanak Shilledar wrote: > > > created spi0 node with fixed clock. the spi0 node > > > uses synopsis designware driver and has the following > > > compatible "snps,dw-apb-ssi". the spi0 node is connected > > > to a SPI NOR flash pad which is left unpopulated on the back > > > side of the board. > > > > > > Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com> > > > --- > > > Changes in v2: > > > - Separated from a single patch file > > > --- > > > .../boot/dts/thead/th1520-beaglev-ahead.dts | 9 +++++++++ > > > .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ > > > .../riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 5 +++++ > > > > Didn't you say there was a flash on one of these two boards? > > > > > arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++ > > > 4 files changed, 34 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > index d9b4de9e4757..3103b74e0288 100644 > > > --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts > > > @@ -17,6 +17,7 @@ aliases { > > > gpio1 = &gpio1; > > > gpio2 = &gpio2; > > > gpio3 = &gpio3; > > > + spi0 = &spi0; > > > > "spi" would sort after "serial". > > > > > serial0 = &uart0; > > > serial1 = &uart1; > > > serial2 = &uart2; > > > @@ -52,6 +53,10 @@ &sdhci_clk { > > > clock-frequency = <198000000>; > > > }; > > > > > > +&spi_clk { > > > + clock-frequency = <396000000>; > > > +}; > > > > I'm pretty sceptical about adding more of these fixed clocks, rather > > than waiting for the clock driver. Drew, what do you think? Should we > > just add one more to your fixup list or would you rather delay? Guess it > > depends on how long more you think that clock driver is likely to take. > > I think the clk driver [1] is in good shape but it has not been reviewed > by the clk maintainer yet. Thus it is hard to predict any timeline for > it getting merged. > > SPI support doesn't require any driver changes so I'd be inclined to > allow the fixed clock in this case. It will be simple to change it over > to a real clock once the clk driver is upstream. > > Acked-by: Drew Fustini <drew@pdp7.com> > > Thanks, > Drew Sorry, I meant to include the link to the most recent clk series: https://lore.kernel.org/linux-riscv/20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com/ -Drew
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index d9b4de9e4757..3103b74e0288 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -17,6 +17,7 @@ aliases { gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; + spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -52,6 +53,10 @@ &sdhci_clk { clock-frequency = <198000000>; }; +&spi_clk { + clock-frequency = <396000000>; +}; + &uart_sclk { clock-frequency = <100000000>; }; @@ -79,3 +84,7 @@ &sdio0 { &uart0 { status = "okay"; }; + +&spi0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1365d3a512a3..6939bd36560c 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -33,6 +33,10 @@ &sdhci_clk { clock-frequency = <198000000>; }; +&spi_clk { + clock-frequency = <396000000>; +}; + &uart_sclk { clock-frequency = <100000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 9a3884a73e13..14b06dd81a9a 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -14,6 +14,7 @@ aliases { gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; + spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -30,3 +31,7 @@ chosen { &uart0 { status = "okay"; }; + +&spi0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d2fa25839012..f962de663e7e 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -140,6 +140,12 @@ apb_clk: apb-clk-clock { #clock-cells = <0>; }; + spi_clk: spi-clock { + compatible = "fixed-clock"; + clock-output-names = "spi_clk"; + #clock-cells = <0>; + }; + uart_sclk: uart-sclk-clock { compatible = "fixed-clock"; clock-output-names = "uart_sclk"; @@ -183,6 +189,16 @@ clint: timer@ffdc000000 { <&cpu3_intc 3>, <&cpu3_intc 7>; }; + spi0: spi@ffe700c000 { + compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; + reg = <0xff 0xe700c000 0x0 0x1000>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&spi_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart0: serial@ffe7014000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7014000 0x0 0x100>;
created spi0 node with fixed clock. the spi0 node uses synopsis designware driver and has the following compatible "snps,dw-apb-ssi". the spi0 node is connected to a SPI NOR flash pad which is left unpopulated on the back side of the board. Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com> --- Changes in v2: - Separated from a single patch file --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 9 +++++++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ .../riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 5 +++++ arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++ 4 files changed, 34 insertions(+)