@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,ipq5332.h>
/ {
interrupt-parent = <&intc>;
@@ -208,6 +209,7 @@ gcc: clock-controller@1800000 {
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
<0>,
@@ -327,11 +329,9 @@ usb: usb@8af8800 {
"dm_hs_phy_irq";
clocks = <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_SNOC_USB_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "core",
- "iface",
"sleep",
"mock_utmi";
@@ -342,6 +342,9 @@ usb: usb@8af8800 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>,
+ <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
+ interconnect-names = "usb-ddr", "apps-usb";
status = "disabled";
IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. Linux itself handles these clocks. However, these should not be exposed as just clocks and align with other Qualcomm SoCs that handle these clocks from a interconnect provider. Hence include icc provider capability to the gcc node so that peripherals can use the interconnect facility to enable these clocks. Change USB to use the icc-clk framework for the iface clock. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)