diff mbox

[v6,10/19] cputlb: add assert_cpu_is_self checks

Message ID 20161109145748.27282-11-alex.bennee@linaro.org
State New
Headers show

Commit Message

Alex Bennée Nov. 9, 2016, 2:57 p.m. UTC 
For SoftMMU the TLB flushes are an example of a task that can be
triggered on one vCPU by another. To deal with this properly we need to
use safe work to ensure these changes are done safely. The new assert
can be enabled while debugging to catch these cases.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
 cputlb.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

-- 
2.10.1

Comments

Richard Henderson Nov. 10, 2016, 4:39 p.m. UTC | #1 
On 11/09/2016 03:57 PM, Alex Bennée wrote:
> For SoftMMU the TLB flushes are an example of a task that can be

> triggered on one vCPU by another. To deal with this properly we need to

> use safe work to ensure these changes are done safely. The new assert

> can be enabled while debugging to catch these cases.

>

> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

> ---

>  cputlb.c | 15 +++++++++++++++

>  1 file changed, 15 insertions(+)


Reviewed-by: Richard Henderson <rth@twiddle.net>



r~
diff mbox

Patch

diff --git a/cputlb.c b/cputlb.c
index c6e34f4..30c7c37 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -58,6 +58,12 @@ 
     } \
 } while (0)
 
+#define assert_cpu_is_self(this_cpu) do {                         \
+        if (DEBUG_TLB_GATE) {                                     \
+            g_assert(!cpu->created || qemu_cpu_is_self(cpu));     \
+        }                                                         \
+    } while (0)
+
 /* statistics */
 int tlb_flush_count;
 
@@ -77,6 +83,7 @@  void tlb_flush(CPUState *cpu, int flush_global)
 {
     CPUArchState *env = cpu->env_ptr;
 
+    assert_cpu_is_self(cpu);
     tlb_debug("(%d)\n", flush_global);
 
     memset(env->tlb_table, -1, sizeof(env->tlb_table));
@@ -93,6 +100,7 @@  static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
 {
     CPUArchState *env = cpu->env_ptr;
 
+    assert_cpu_is_self(cpu);
     tlb_debug("start\n");
 
     for (;;) {
@@ -137,6 +145,7 @@  void tlb_flush_page(CPUState *cpu, target_ulong addr)
     int i;
     int mmu_idx;
 
+    assert_cpu_is_self(cpu);
     tlb_debug("page :" TARGET_FMT_lx "\n", addr);
 
     /* Check if we need to flush due to large pages.  */
@@ -174,6 +183,7 @@  void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
 
     va_start(argp, addr);
 
+    assert_cpu_is_self(cpu);
     tlb_debug("addr "TARGET_FMT_lx"\n", addr);
 
     /* Check if we need to flush due to large pages.  */
@@ -262,6 +272,8 @@  void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
 
     int mmu_idx;
 
+    assert_cpu_is_self(cpu);
+
     env = cpu->env_ptr;
     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
         unsigned int i;
@@ -293,6 +305,8 @@  void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
     int i;
     int mmu_idx;
 
+    assert_cpu_is_self(cpu);
+
     vaddr &= TARGET_PAGE_MASK;
     i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
@@ -352,6 +366,7 @@  void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
     unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
     int asidx = cpu_asidx_from_attrs(cpu, attrs);
 
+    assert_cpu_is_self(cpu);
     assert(size >= TARGET_PAGE_SIZE);
     if (size != TARGET_PAGE_SIZE) {
         tlb_add_large_page(env, vaddr, size);