diff mbox series

rteval: measurement: Change latency flag to latency_test

Message ID 20240726183237.44769-1-crwood@redhat.com
State New
Headers show
Series rteval: measurement: Change latency flag to latency_test | expand

Commit Message

Crystal Wood July 26, 2024, 6:32 p.m. UTC 
As requested by John, change the name of the latency flag to avoid
looking like it holds an actual latency value.

Signed-off-by: Crystal Wood <crwood@redhat.com>
---
 rteval/modules/__init__.py               | 14 +++++++-------
 rteval/modules/measurement/cyclictest.py |  2 +-
 rteval/modules/measurement/timerlat.py   |  2 +-
 3 files changed, 9 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/rteval/modules/__init__.py b/rteval/modules/__init__.py
index 2a4eafae71c7..d7792108d5b8 100644
--- a/rteval/modules/__init__.py
+++ b/rteval/modules/__init__.py
@@ -40,7 +40,7 @@  class rtevalModulePrototype(threading.Thread):
                          "finished": threading.Event()}
         self._donotrun = False
         self._exclusive = False
-        self._latency = False
+        self._latency_test = False
         self.__timestamps = {}
         self.__sleeptime = 2.0
 
@@ -68,9 +68,9 @@  class rtevalModulePrototype(threading.Thread):
         self._exclusive = True
 
 
-    def set_latency(self):
+    def set_latency_test(self):
         """ Sets the module as an exclusive latency measurer """
-        self._latency = True
+        self._latency_test = True
 
 
     def set_donotrun(self):
@@ -418,14 +418,14 @@  class RtEvalModules:
 
         self._logger.log(Log.INFO, f"Preparing {self._module_type} modules")
         exclusive = 0
-        latency = False
+        latency_test = False
         for (modname, mod) in self.__modules:
             if mod.is_exclusive() and mod.WorkloadWillRun():
                 exclusive += 1
-            if mod._latency:
-                if latency:
+            if mod._latency_test:
+                if latency_test:
                     raise RuntimeError("More than one exclusive latency test")
-                latency = True
+                latency_test = True
         for (modname, mod) in self.__modules:
             if exclusive >= 1:
                 if exclusive != 1:
diff --git a/rteval/modules/measurement/cyclictest.py b/rteval/modules/measurement/cyclictest.py
index a9f5b0c4fba7..d919058e927f 100644
--- a/rteval/modules/measurement/cyclictest.py
+++ b/rteval/modules/measurement/cyclictest.py
@@ -216,7 +216,7 @@  class Cyclictest(rtevalModulePrototype):
         self.__started = False
         self.__cyclicoutput = None
         self.__breaktraceval = None
-        self.set_latency()
+        self.set_latency_test()
 
 
     @staticmethod
diff --git a/rteval/modules/measurement/timerlat.py b/rteval/modules/measurement/timerlat.py
index e4b80c33552e..92bc07051aa1 100644
--- a/rteval/modules/measurement/timerlat.py
+++ b/rteval/modules/measurement/timerlat.py
@@ -216,7 +216,7 @@  class Timerlat(rtevalModulePrototype):
                                                   logfnc=self._log)
         self.__timerlatdata['system'].description = (f"({self.__numcores} cores) ") + info['0']['model name']
         self._log(Log.DEBUG, f"system using {self.__numcores} cpu cores")
-        self.set_latency()
+        self.set_latency_test()
 
 
     def _WorkloadSetup(self):