diff mbox series

[04/10] clk: qcom: dispcc-sm8450: Add SM8475 support

Message ID 20240731175919.20333-5-danila@jiaxyga.com
State New
Headers show
Series Add SM8475 clock controller drivers | expand

Commit Message

Danila Tikhonov July 31, 2024, 5:59 p.m. UTC 
Add support to the SM8475 display clock controller by extending the
SM8450 display clock controller, which is almost identical but has
some minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/clk/qcom/Kconfig         |  2 +-
 drivers/clk/qcom/dispcc-sm8450.c | 49 ++++++++++++++++++++++++++++++--
 2 files changed, 47 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index decb41c4a58e..702de741cedd 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -924,7 +924,7 @@  config SM_DISPCC_8450
 	depends on SM_GCC_8450
 	help
 	  Support for the display clock controller on Qualcomm Technologies, Inc
-	  SM8450 devices.
+	  SM8450 or SM8475 devices.
 	  Say Y if you want to support display devices and functionality such as
 	  splash screen.
 
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index d1d3f60789ee..cef38cdd7318 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -75,7 +75,7 @@  static const struct pll_vco lucid_evo_vco[] = {
 	{ 249600000, 2000000000, 0 },
 };
 
-static const struct alpha_pll_config disp_cc_pll0_config = {
+static struct alpha_pll_config disp_cc_pll0_config = {
 	.l = 0xD,
 	.alpha = 0x6492,
 	.config_ctl_val = 0x20485699,
@@ -85,6 +85,15 @@  static const struct alpha_pll_config disp_cc_pll0_config = {
 	.user_ctl_hi_val = 0x00000805,
 };
 
+static struct clk_init_data disp_cc_pll0_sm8475_init = {
+	.name = "disp_cc_pll0",
+	.parent_data = &(const struct clk_parent_data) {
+		.index = DT_BI_TCXO,
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_reset_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll disp_cc_pll0 = {
 	.offset = 0x0,
 	.vco_table = lucid_evo_vco,
@@ -102,7 +111,7 @@  static struct clk_alpha_pll disp_cc_pll0 = {
 	},
 };
 
-static const struct alpha_pll_config disp_cc_pll1_config = {
+static struct alpha_pll_config disp_cc_pll1_config = {
 	.l = 0x1F,
 	.alpha = 0x4000,
 	.config_ctl_val = 0x20485699,
@@ -112,6 +121,15 @@  static const struct alpha_pll_config disp_cc_pll1_config = {
 	.user_ctl_hi_val = 0x00000805,
 };
 
+static struct clk_init_data disp_cc_pll1_sm8475_init = {
+	.name = "disp_cc_pll1",
+	.parent_data = &(const struct clk_parent_data) {
+		.index = DT_BI_TCXO,
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_reset_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll disp_cc_pll1 = {
 	.offset = 0x1000,
 	.vco_table = lucid_evo_vco,
@@ -1746,6 +1764,7 @@  static struct qcom_cc_desc disp_cc_sm8450_desc = {
 
 static const struct of_device_id disp_cc_sm8450_match_table[] = {
 	{ .compatible = "qcom,sm8450-dispcc" },
+	{ .compatible = "qcom,sm8475-dispcc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);
@@ -1769,6 +1788,30 @@  static int disp_cc_sm8450_probe(struct platform_device *pdev)
 		goto err_put_rpm;
 	}
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) {
+		/* Update DISPCC PLL0 Config */
+		disp_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
+		disp_cc_pll0_config.test_ctl_val = 0x00000000;
+		disp_cc_pll0_config.test_ctl_hi_val = 0x00000003;
+		disp_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
+		disp_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
+		disp_cc_pll0_config.user_ctl_hi_val = 0x00000005;
+
+		disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		disp_cc_pll0.clkr.hw.init = &disp_cc_pll0_sm8475_init;
+
+		/* Update DISPCC PLL1 Config */
+		disp_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
+		disp_cc_pll1_config.test_ctl_val = 0x00000000;
+		disp_cc_pll1_config.test_ctl_hi_val = 0x00000003;
+		disp_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
+		disp_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
+		disp_cc_pll1_config.user_ctl_hi_val = 0x00000005;
+
+		disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		disp_cc_pll1.clkr.hw.init = &disp_cc_pll1_sm8475_init;
+	}
+
 	clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
 
@@ -1802,5 +1845,5 @@  static struct platform_driver disp_cc_sm8450_driver = {
 
 module_platform_driver(disp_cc_sm8450_driver);
 
-MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
+MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL");