[Linaro-uefi,06/27] Hisilicon/PCIeInit: fix PciePcsInit bug

Message ID 1478785950-24197-7-git-send-email-heyi.guo@linaro.org
State Superseded
Headers show

Commit Message

gary guo Nov. 10, 2016, 1:52 p.m.
There are 8 phys at each Pcie Controller, so it should be set
for 8 times loop.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 8 +++++---
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 ++
 2 files changed, 7 insertions(+), 3 deletions(-)

Comments

Leif Lindholm Nov. 10, 2016, 4:01 p.m. | #1
On Thu, Nov 10, 2016 at 09:52:10PM +0800, Heyi Guo wrote:
> There are 8 phys at each Pcie Controller, so it should be set
> for 8 times loop.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 8 +++++---
>  Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 ++
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> index 88810ce..4519cd0 100644
> --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> @@ -466,9 +466,11 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
>      UINT32 Value = 0;
>      if (0x1610 == soctype)
>      {
> -        RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
> -        Value |= (1 << 20);
> -        RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
> +        for (i = 0; i < PcieMaxLanNum; i++) {
> +            RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
> +            Value |= (1 << 20); //bit 20: rxvalid enable
> +            RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
> +        }
>          PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
>          RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
>      }
> diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
> index 1e8db97..9671c57 100644
> --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
> +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
> @@ -68,6 +68,8 @@
>  #define PCIE_BAR_TYPE_64            (2)
>  #define PCIE_BAR_PREFETCH_MODE      (1)
>  
> +#define PCS_SDS_CFG_REG            0x204
> +#define SDS_CFG_STRIDE             0x4
>  #define RegWrite(addr,data)            MmioWrite32((addr), (data))
>  #define RegRead(addr,data)             ((data) = MmioRead32 (addr))
>  
> -- 
> 1.9.1
>

Patch

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index 88810ce..4519cd0 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -466,9 +466,11 @@  VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
     UINT32 Value = 0;
     if (0x1610 == soctype)
     {
-        RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
-        Value |= (1 << 20);
-        RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+        for (i = 0; i < PcieMaxLanNum; i++) {
+            RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+            Value |= (1 << 20); //bit 20: rxvalid enable
+            RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+        }
         PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
         RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
     }
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
index 1e8db97..9671c57 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -68,6 +68,8 @@ 
 #define PCIE_BAR_TYPE_64            (2)
 #define PCIE_BAR_PREFETCH_MODE      (1)
 
+#define PCS_SDS_CFG_REG            0x204
+#define SDS_CFG_STRIDE             0x4
 #define RegWrite(addr,data)            MmioWrite32((addr), (data))
 #define RegRead(addr,data)             ((data) = MmioRead32 (addr))