From patchwork Thu Nov 10 13:52:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 81655 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp739263qge; Thu, 10 Nov 2016 06:02:50 -0800 (PST) X-Received: by 10.55.23.213 with SMTP id 82mr5677939qkx.40.1478786570520; Thu, 10 Nov 2016 06:02:50 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id h49si3436647qtb.41.2016.11.10.06.02.50; Thu, 10 Nov 2016 06:02:50 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3691E60851; Thu, 10 Nov 2016 14:02:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 4C5A76080A; Thu, 10 Nov 2016 13:57:16 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A750160D9A; Thu, 10 Nov 2016 13:57:11 +0000 (UTC) Received: from mail-pf0-f173.google.com (mail-pf0-f173.google.com [209.85.192.173]) by lists.linaro.org (Postfix) with ESMTPS id 169076080A for ; Thu, 10 Nov 2016 13:53:35 +0000 (UTC) Received: by mail-pf0-f173.google.com with SMTP id n85so147121044pfi.1 for ; Thu, 10 Nov 2016 05:53:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f1pF8OkoPxiymWct+cZGN8dkiRd6Zr9q3RCqo3w9uT4=; b=GQETt6gNVr3kt1ey8oiQhYRHC5hj2OSGUxgA5P0LPC54sdOH/Ora0JBfQLiRaodRpG GVkaYRbOsz0cJLTA8m/IXu4XZ9qKHM9XqTseTi12SqYSmoDZhiGE4/Nc7Jqf4w+21Nd4 HZoPPu6umN/I5AiM9wQqGYbiKOtkQluZxd/UCLpcYLpdV6UqJMc1CNtJHlFKbVi7Z2dh msaWa13veV9LOICN76fy90qiKZRAUObMOOdPxS5lZDV39BPkOJoWy6U/gfRGzpcD3TXm 0iJzJF9UvcTNnPSZf/xCoNfC+jiuxGIrz45wDGbKFfKOe9hM/u3L7NlqdwunENPz7nlm 4RNQ== X-Gm-Message-State: ABUngvdPiP4a4z+43sOU0c4Wc1ot4cDG67xgBnIy7YeC0lqkxpFCRXAA2YA6lDVh5dGqd8UPAwo= X-Received: by 10.98.44.212 with SMTP id s203mr10337884pfs.84.1478786014377; Thu, 10 Nov 2016 05:53:34 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g78sm7625705pfe.19.2016.11.10.05.53.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Nov 2016 05:53:33 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 10 Nov 2016 21:52:10 +0800 Message-Id: <1478785950-24197-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> References: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 06/27] Hisilicon/PCIeInit: fix PciePcsInit bug X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" There are 8 phys at each Pcie Controller, so it should be set for 8 times loop. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 8 +++++--- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 88810ce..4519cd0 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -466,9 +466,11 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); - Value |= (1 << 20); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); + for (i = 0; i < PcieMaxLanNum; i++) { + RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + Value |= (1 << 20); //bit 20: rxvalid enable + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); } diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 1e8db97..9671c57 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -68,6 +68,8 @@ #define PCIE_BAR_TYPE_64 (2) #define PCIE_BAR_PREFETCH_MODE (1) +#define PCS_SDS_CFG_REG 0x204 +#define SDS_CFG_STRIDE 0x4 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr))