@@ -1468,7 +1468,7 @@ static int ath12k_dp_cmem_init(struct ath12k_base *ab,
struct ath12k_dp *dp,
enum ath12k_dp_desc_type type)
{
- u32 cmem_base;
+ u32 cmem_base, data;
int i, start, end;
cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
@@ -1489,9 +1489,11 @@ static int ath12k_dp_cmem_init(struct ath12k_base *ab,
}
/* Write to PPT in CMEM */
- for (i = start; i < end; i++)
- ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
- dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET);
+ for (i = start; i < end; i++) {
+ data = dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET;
+ ath12k_hif_cmem_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
+ data);
+ }
return 0;
}
@@ -12,6 +12,8 @@
struct ath12k_hif_ops {
u32 (*read32)(struct ath12k_base *ab, u32 address);
void (*write32)(struct ath12k_base *ab, u32 address, u32 data);
+ u32 (*cmem_read32)(struct ath12k_base *sc, u32 address);
+ void (*cmem_write32)(struct ath12k_base *sc, u32 address, u32 data);
void (*irq_enable)(struct ath12k_base *ab);
void (*irq_disable)(struct ath12k_base *ab);
int (*start)(struct ath12k_base *ab);
@@ -132,6 +134,17 @@ static inline void ath12k_hif_write32(struct ath12k_base *ab, u32 address,
ab->hif.ops->write32(ab, address, data);
}
+static inline u32 ath12k_hif_cmem_read32(struct ath12k_base *ab, u32 address)
+{
+ return ab->hif.ops->cmem_read32(ab, address);
+}
+
+static inline void ath12k_hif_cmem_write32(struct ath12k_base *ab, u32 address,
+ u32 data)
+{
+ ab->hif.ops->cmem_write32(ab, address, data);
+}
+
static inline int ath12k_hif_power_up(struct ath12k_base *ab)
{
if (!ab->hif.ops->power_up)
@@ -1316,6 +1316,8 @@ static const struct ath12k_hif_ops ath12k_pci_hif_ops = {
.stop = ath12k_pci_stop,
.read32 = ath12k_pci_read32,
.write32 = ath12k_pci_write32,
+ .cmem_read32 = ath12k_pci_read32,
+ .cmem_write32 = ath12k_pci_write32,
.power_down = ath12k_pci_power_down,
.power_up = ath12k_pci_power_up,
.suspend = ath12k_pci_hif_suspend,