| Message ID | 20240814161451.32119-1-laurent.pinchart@ideasonboard.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4] arm64: dts: imx8mp: Add DT nodes for the two ISPs | expand |
Hi Alexander, On Thu, Aug 15, 2024 at 02:05:39PM +0200, Alexander Stein wrote: > Am Mittwoch, 14. August 2024, 18:14:51 CEST schrieb Laurent Pinchart: > > From: Paul Elder <paul.elder@ideasonboard.com> > > > > The ISP supports both CSI and parallel interfaces, where port 0 > > corresponds to the former and port 1 corresponds to the latter. Since > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI > > receiver, set them both to port 1. > > > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > --- > > Changes since v3: > > > > - Add comment regarding the IMX8MP_CLK_MEDIA_ISP clock rate > > - Fix assigned-clock-rates > > - Dropping Tested-by as the clock configuration has changed > > > > Changes since v2: > > > > - Assign clock parent and frequency in blk-ctrl > > > > Changes since v1: > > > > - Fix clock ordering > > - Add #address-cells and #size-cells to ports nodes > > --- > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++++- > > 1 file changed, 55 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > index d9b5c40f6460..f3531cfb0d79 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint { > > }; > > }; > > > > + isp_0: isp@32e10000 { > > + compatible = "fsl,imx8mp-isp"; > > + reg = <0x32e10000 0x10000>; > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > + clock-names = "isp", "aclk", "hclk"; > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > + fsl,blk-ctrl = <&media_blk_ctrl 0>; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > + isp_1: isp@32e20000 { > > + compatible = "fsl,imx8mp-isp"; > > + reg = <0x32e20000 0x10000>; > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > + clock-names = "isp", "aclk", "hclk"; > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > + fsl,blk-ctrl = <&media_blk_ctrl 1>; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > dewarp: dwe@32e30000 { > > compatible = "nxp,imx8mp-dw100"; > > reg = <0x32e30000 0x10000>; > > @@ -1869,17 +1913,26 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > > clock-names = "apb", "axi", "cam1", "cam2", > > "disp1", "disp2", "isp", "phy"; > > > > + /* > > + * The ISP maximum frequency is 400MHz in normal mode > > + * and 500MHz in overdrive mode. The 400MHz operating > > + * point hasn't been successfully tested yet, so set > > + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. > > + */ > > assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, > > <&clk IMX8MP_CLK_MEDIA_APB>, > > <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, > > <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > > + <&clk IMX8MP_CLK_MEDIA_ISP>, > > <&clk IMX8MP_VIDEO_PLL1>; > > assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > > <&clk IMX8MP_SYS_PLL1_800M>, > > <&clk IMX8MP_VIDEO_PLL1_OUT>, > > - <&clk IMX8MP_VIDEO_PLL1_OUT>; > > + <&clk IMX8MP_VIDEO_PLL1_OUT>, > > + <&clk IMX8MP_SYS_PLL2_500M>; > > assigned-clock-rates = <500000000>, <200000000>, > > - <0>, <0>, <1039500000>; > > + <0>, <0>, <500000000>, > > + <1039500000>; > > Unfortunately for some reason this reparenting doesn't work (on my platform). > 'media_isp' is still below IMX8MP_CLK_24M. > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > mipi_dsi_esc_rx 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > media_isp 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > media_isp_root_clk 0 0 0 24000000 0 0 50000 N 32e10000.isp isp Hmmm... I get sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > I have to add this diff for isp_0 (and isp_1 if you use it): > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -1683,6 +1683,9 @@ isp_0: isp@32e10000 { > clock-names = "isp", "aclk", "hclk"; > power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > fsl,blk-ctrl = <&media_blk_ctrl 0>; > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > + assigned-clock-rates = <500000000>; > status = "disabled"; > > ports { > > Now clock is setup properly: > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp I'm not sure why that's the case, I don't have assigned-clock* properties in the ISP nodes in my device tree and things still work properly. Would you be able to investigate ? > > #power-domain-cells = <1>; > > > > lvds_bridge: bridge@5c { > > > > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba > > prerequisite-patch-id: ad2bbccf3b0f27415fb14851cec52c431ccb354f
On Sat, Aug 17, 2024 at 1:26 PM Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > > Hi Alexander, > > On Thu, Aug 15, 2024 at 02:05:39PM +0200, Alexander Stein wrote: > > Am Mittwoch, 14. August 2024, 18:14:51 CEST schrieb Laurent Pinchart: > > > From: Paul Elder <paul.elder@ideasonboard.com> > > > > > > The ISP supports both CSI and parallel interfaces, where port 0 > > > corresponds to the former and port 1 corresponds to the latter. Since > > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI > > > receiver, set them both to port 1. > > > > > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > --- > > > Changes since v3: > > > > > > - Add comment regarding the IMX8MP_CLK_MEDIA_ISP clock rate > > > - Fix assigned-clock-rates > > > - Dropping Tested-by as the clock configuration has changed > > > > > > Changes since v2: > > > > > > - Assign clock parent and frequency in blk-ctrl > > > > > > Changes since v1: > > > > > > - Fix clock ordering > > > - Add #address-cells and #size-cells to ports nodes > > > --- > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++++- > > > 1 file changed, 55 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > index d9b5c40f6460..f3531cfb0d79 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint { > > > }; > > > }; > > > > > > + isp_0: isp@32e10000 { > > > + compatible = "fsl,imx8mp-isp"; > > > + reg = <0x32e10000 0x10000>; > > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > + clock-names = "isp", "aclk", "hclk"; > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > + fsl,blk-ctrl = <&media_blk_ctrl 0>; > > > + status = "disabled"; > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@1 { > > > + reg = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > + isp_1: isp@32e20000 { > > > + compatible = "fsl,imx8mp-isp"; > > > + reg = <0x32e20000 0x10000>; > > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > + clock-names = "isp", "aclk", "hclk"; > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > + fsl,blk-ctrl = <&media_blk_ctrl 1>; > > > + status = "disabled"; > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@1 { > > > + reg = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > dewarp: dwe@32e30000 { > > > compatible = "nxp,imx8mp-dw100"; > > > reg = <0x32e30000 0x10000>; > > > @@ -1869,17 +1913,26 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > > > clock-names = "apb", "axi", "cam1", "cam2", > > > "disp1", "disp2", "isp", "phy"; > > > > > > + /* > > > + * The ISP maximum frequency is 400MHz in normal mode > > > + * and 500MHz in overdrive mode. The 400MHz operating > > > + * point hasn't been successfully tested yet, so set > > > + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. > > > + */ > > > assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, > > > <&clk IMX8MP_CLK_MEDIA_APB>, > > > <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, > > > <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > > > + <&clk IMX8MP_CLK_MEDIA_ISP>, > > > <&clk IMX8MP_VIDEO_PLL1>; > > > assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > > > <&clk IMX8MP_SYS_PLL1_800M>, > > > <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > - <&clk IMX8MP_VIDEO_PLL1_OUT>; > > > + <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > + <&clk IMX8MP_SYS_PLL2_500M>; > > > assigned-clock-rates = <500000000>, <200000000>, > > > - <0>, <0>, <1039500000>; > > > + <0>, <0>, <500000000>, > > > + <1039500000>; > > > > Unfortunately for some reason this reparenting doesn't work (on my platform). > > 'media_isp' is still below IMX8MP_CLK_24M. > > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > > mipi_dsi_esc_rx 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > > media_isp 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > > media_isp_root_clk 0 0 0 24000000 0 0 50000 N 32e10000.isp isp > > Hmmm... I get > > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > > > I have to add this diff for isp_0 (and isp_1 if you use it): > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -1683,6 +1683,9 @@ isp_0: isp@32e10000 { > > clock-names = "isp", "aclk", "hclk"; > > power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > fsl,blk-ctrl = <&media_blk_ctrl 0>; > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > + assigned-clock-rates = <500000000>; > > status = "disabled"; > > > > ports { > > > > Now clock is setup properly: > > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > > I'm not sure why that's the case, I don't have assigned-clock* > properties in the ISP nodes in my device tree and things still work > properly. Would you be able to investigate ? For what it's worth, when I remove the extra <0> clock reference on my board like: --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1927,7 +1927,7 @@ media_blk_ctrl: blk-ctrl@32ec0000 { <&clk IMX8MP_VIDEO_PLL1_OUT>, <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>, <200000000>, - <0>, <0>, <0>, <500000000>, + <0>, <0>, <500000000>, <1039500000>; #power-domain-cells = <1>; I am able to get: sys_pll2_500m 1 1 0 500000000 0 0 50000 Y deviceless no_connection_id media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp The video pll is also set to 1039500000 adam > > > > #power-domain-cells = <1>; > > > > > > lvds_bridge: bridge@5c { > > > > > > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba > > > prerequisite-patch-id: ad2bbccf3b0f27415fb14851cec52c431ccb354f > > -- > Regards, > > Laurent Pinchart
Hi Laurent, Am Samstag, 17. August 2024, 20:25:46 CEST schrieb Laurent Pinchart: > Hi Alexander, > > On Thu, Aug 15, 2024 at 02:05:39PM +0200, Alexander Stein wrote: > > Am Mittwoch, 14. August 2024, 18:14:51 CEST schrieb Laurent Pinchart: > > > From: Paul Elder <paul.elder@ideasonboard.com> > > > > > > The ISP supports both CSI and parallel interfaces, where port 0 > > > corresponds to the former and port 1 corresponds to the latter. Since > > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI > > > receiver, set them both to port 1. > > > > > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > --- > > > Changes since v3: > > > > > > - Add comment regarding the IMX8MP_CLK_MEDIA_ISP clock rate > > > - Fix assigned-clock-rates > > > - Dropping Tested-by as the clock configuration has changed > > > > > > Changes since v2: > > > > > > - Assign clock parent and frequency in blk-ctrl > > > > > > Changes since v1: > > > > > > - Fix clock ordering > > > - Add #address-cells and #size-cells to ports nodes > > > --- > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++++- > > > 1 file changed, 55 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > index d9b5c40f6460..f3531cfb0d79 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint { > > > }; > > > }; > > > > > > + isp_0: isp@32e10000 { > > > + compatible = "fsl,imx8mp-isp"; > > > + reg = <0x32e10000 0x10000>; > > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > + clock-names = "isp", "aclk", "hclk"; > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > + fsl,blk-ctrl = <&media_blk_ctrl 0>; > > > + status = "disabled"; > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@1 { > > > + reg = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > + isp_1: isp@32e20000 { > > > + compatible = "fsl,imx8mp-isp"; > > > + reg = <0x32e20000 0x10000>; > > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > + clock-names = "isp", "aclk", "hclk"; > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > + fsl,blk-ctrl = <&media_blk_ctrl 1>; > > > + status = "disabled"; > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@1 { > > > + reg = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > dewarp: dwe@32e30000 { > > > compatible = "nxp,imx8mp-dw100"; > > > reg = <0x32e30000 0x10000>; > > > @@ -1869,17 +1913,26 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > > > clock-names = "apb", "axi", "cam1", "cam2", > > > "disp1", "disp2", "isp", "phy"; > > > > > > + /* > > > + * The ISP maximum frequency is 400MHz in normal mode > > > + * and 500MHz in overdrive mode. The 400MHz operating > > > + * point hasn't been successfully tested yet, so set > > > + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. > > > + */ > > > assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, > > > <&clk IMX8MP_CLK_MEDIA_APB>, > > > <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, > > > <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > > > + <&clk IMX8MP_CLK_MEDIA_ISP>, > > > <&clk IMX8MP_VIDEO_PLL1>; > > > assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > > > <&clk IMX8MP_SYS_PLL1_800M>, > > > <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > - <&clk IMX8MP_VIDEO_PLL1_OUT>; > > > + <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > + <&clk IMX8MP_SYS_PLL2_500M>; > > > assigned-clock-rates = <500000000>, <200000000>, > > > - <0>, <0>, <1039500000>; > > > + <0>, <0>, <500000000>, > > > + <1039500000>; > > > > Unfortunately for some reason this reparenting doesn't work (on my platform). > > 'media_isp' is still below IMX8MP_CLK_24M. > > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > > mipi_dsi_esc_rx 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > > media_isp 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > > media_isp_root_clk 0 0 0 24000000 0 0 50000 N 32e10000.isp isp > > Hmmm... I get > > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > > > I have to add this diff for isp_0 (and isp_1 if you use it): > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -1683,6 +1683,9 @@ isp_0: isp@32e10000 { > > clock-names = "isp", "aclk", "hclk"; > > power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > fsl,blk-ctrl = <&media_blk_ctrl 0>; > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > + assigned-clock-rates = <500000000>; > > status = "disabled"; > > > > ports { > > > > Now clock is setup properly: > > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > > I'm not sure why that's the case, I don't have assigned-clock* > properties in the ISP nodes in my device tree and things still work > properly. Would you be able to investigate ? I had a local board-specific overwrite in place for node 'media_blk_ctrl' I forgot about... So this patch does what it is supposed to do: Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Hi Adam, On Sun, Aug 18, 2024 at 01:33:26PM -0500, Adam Ford wrote: > On Sat, Aug 17, 2024 at 1:26 PM Laurent Pinchart wrote: > > On Thu, Aug 15, 2024 at 02:05:39PM +0200, Alexander Stein wrote: > > > Am Mittwoch, 14. August 2024, 18:14:51 CEST schrieb Laurent Pinchart: > > > > From: Paul Elder <paul.elder@ideasonboard.com> > > > > > > > > The ISP supports both CSI and parallel interfaces, where port 0 > > > > corresponds to the former and port 1 corresponds to the latter. Since > > > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI > > > > receiver, set them both to port 1. > > > > > > > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > > --- > > > > Changes since v3: > > > > > > > > - Add comment regarding the IMX8MP_CLK_MEDIA_ISP clock rate > > > > - Fix assigned-clock-rates > > > > - Dropping Tested-by as the clock configuration has changed > > > > > > > > Changes since v2: > > > > > > > > - Assign clock parent and frequency in blk-ctrl > > > > > > > > Changes since v1: > > > > > > > > - Fix clock ordering > > > > - Add #address-cells and #size-cells to ports nodes > > > > --- > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++++- > > > > 1 file changed, 55 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > > index d9b5c40f6460..f3531cfb0d79 100644 > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint { > > > > }; > > > > }; > > > > > > > > + isp_0: isp@32e10000 { > > > > + compatible = "fsl,imx8mp-isp"; > > > > + reg = <0x32e10000 0x10000>; > > > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > > + clock-names = "isp", "aclk", "hclk"; > > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > > + fsl,blk-ctrl = <&media_blk_ctrl 0>; > > > > + status = "disabled"; > > > > + > > > > + ports { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + port@1 { > > > > + reg = <1>; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > + isp_1: isp@32e20000 { > > > > + compatible = "fsl,imx8mp-isp"; > > > > + reg = <0x32e20000 0x10000>; > > > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > > > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; > > > > + clock-names = "isp", "aclk", "hclk"; > > > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > > + fsl,blk-ctrl = <&media_blk_ctrl 1>; > > > > + status = "disabled"; > > > > + > > > > + ports { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + port@1 { > > > > + reg = <1>; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > dewarp: dwe@32e30000 { > > > > compatible = "nxp,imx8mp-dw100"; > > > > reg = <0x32e30000 0x10000>; > > > > @@ -1869,17 +1913,26 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > > > > clock-names = "apb", "axi", "cam1", "cam2", > > > > "disp1", "disp2", "isp", "phy"; > > > > > > > > + /* > > > > + * The ISP maximum frequency is 400MHz in normal mode > > > > + * and 500MHz in overdrive mode. The 400MHz operating > > > > + * point hasn't been successfully tested yet, so set > > > > + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. > > > > + */ > > > > assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, > > > > <&clk IMX8MP_CLK_MEDIA_APB>, > > > > <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, > > > > <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > > > > + <&clk IMX8MP_CLK_MEDIA_ISP>, > > > > <&clk IMX8MP_VIDEO_PLL1>; > > > > assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > > > > <&clk IMX8MP_SYS_PLL1_800M>, > > > > <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > > - <&clk IMX8MP_VIDEO_PLL1_OUT>; > > > > + <&clk IMX8MP_VIDEO_PLL1_OUT>, > > > > + <&clk IMX8MP_SYS_PLL2_500M>; > > > > assigned-clock-rates = <500000000>, <200000000>, > > > > - <0>, <0>, <1039500000>; > > > > + <0>, <0>, <500000000>, > > > > + <1039500000>; > > > > > > Unfortunately for some reason this reparenting doesn't work (on my platform). > > > 'media_isp' is still below IMX8MP_CLK_24M. > > > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > > > mipi_dsi_esc_rx 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > > > media_isp 0 0 0 24000000 0 0 50000 N deviceless no_connection_id > > > media_isp_root_clk 0 0 0 24000000 0 0 50000 N 32e10000.isp isp > > > > Hmmm... I get > > > > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > > > > > I have to add this diff for isp_0 (and isp_1 if you use it): > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > @@ -1683,6 +1683,9 @@ isp_0: isp@32e10000 { > > > clock-names = "isp", "aclk", "hclk"; > > > power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; > > > fsl,blk-ctrl = <&media_blk_ctrl 0>; > > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; > > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > > + assigned-clock-rates = <500000000>; > > > status = "disabled"; > > > > > > ports { > > > > > > Now clock is setup properly: > > > $ grep -B1 media_isp /sys/kernel/debug/clk/clk_summary > > > sys_pll2_500m 3 3 0 500000000 0 0 50000 Y deviceless no_connection_id > > > media_isp 0 0 0 500000000 0 0 50000 N deviceless no_connection_id > > > media_isp_root_clk 0 0 0 500000000 0 0 50000 N 32e10000.isp isp > > > > I'm not sure why that's the case, I don't have assigned-clock* > > properties in the ISP nodes in my device tree and things still work > > properly. Would you be able to investigate ? > > For what it's worth, when I remove the extra <0> clock reference on my > board like: > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -1927,7 +1927,7 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > <&clk IMX8MP_VIDEO_PLL1_OUT>, > <&clk IMX8MP_SYS_PLL2_500M>; > assigned-clock-rates = <500000000>, <200000000>, > - <0>, <0>, <0>, <500000000>, > + <0>, <0>, <500000000>, You're looking at v3, v4 doesn't have the extra 0. > <1039500000>; > #power-domain-cells = <1>; > > > I am able to get: > > sys_pll2_500m 1 1 0 > 500000000 0 0 50000 Y deviceless > no_connection_id > media_isp 0 0 0 > 500000000 0 0 50000 N > deviceless no_connection_id > media_isp_root_clk 0 0 0 > 500000000 0 0 50000 N > 32e10000.isp isp > > > The video pll is also set to 1039500000 > > > > > #power-domain-cells = <1>; > > > > > > > > lvds_bridge: bridge@5c { > > > > > > > > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba > > > > prerequisite-patch-id: ad2bbccf3b0f27415fb14851cec52c431ccb354f
On Wed, Aug 14, 2024 at 07:14:51PM +0300, Laurent Pinchart wrote: > From: Paul Elder <paul.elder@ideasonboard.com> > > The ISP supports both CSI and parallel interfaces, where port 0 > corresponds to the former and port 1 corresponds to the latter. Since > the i.MX8MP's ISPs are connected by the parallel interface to the CSI > receiver, set them both to port 1. > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index d9b5c40f6460..f3531cfb0d79 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1673,6 +1673,50 @@ isi_in_1: endpoint { }; }; + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "isp", "aclk", "hclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + fsl,blk-ctrl = <&media_blk_ctrl 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "isp", "aclk", "hclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + fsl,blk-ctrl = <&media_blk_ctrl 1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + }; + dewarp: dwe@32e30000 { compatible = "nxp,imx8mp-dw100"; reg = <0x32e30000 0x10000>; @@ -1869,17 +1913,26 @@ media_blk_ctrl: blk-ctrl@32ec0000 { clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", "isp", "phy"; + /* + * The ISP maximum frequency is 400MHz in normal mode + * and 500MHz in overdrive mode. The 400MHz operating + * point hasn't been successfully tested yet, so set + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. + */ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, <&clk IMX8MP_CLK_MEDIA_APB>, <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VIDEO_PLL1_OUT>, - <&clk IMX8MP_VIDEO_PLL1_OUT>; + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>, <200000000>, - <0>, <0>, <1039500000>; + <0>, <0>, <500000000>, + <1039500000>; #power-domain-cells = <1>; lvds_bridge: bridge@5c {