diff mbox series

[3/4] clk/qcom: sm6115: add debug data

Message ID 20240819-b4-qcom-clk-dump-v1-3-182cf77c23a2@linaro.org
State Accepted
Commit 9b93eb40496a6c905b2526ec4be2499b922eb127
Headers show
Series clk/qcom: implement clk dump callback | expand

Commit Message

Caleb Connolly Aug. 19, 2024, 7:34 p.m. UTC 
Add "clk dump" support for SM6115.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-sm6115.c | 63 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c
index 8314a0deb348..9057dfe0bb18 100644
--- a/drivers/clk/qcom/clock-sm6115.c
+++ b/drivers/clk/qcom/clock-sm6115.c
@@ -169,8 +169,65 @@  static const struct qcom_reset_map sm6115_gcc_resets[] = {
 static const struct qcom_power_map sm6115_gdscs[] = {
 	[GCC_USB30_PRIM_GDSC] = { 0x1a004 },
 };
 
+static const phys_addr_t sm6115_gpll_addrs[] = {
+	0x01400000, // GCC_GPLL0_MODE
+	0x01401000, // GCC_GPLL1_MODE
+	0x01402000, // GCC_GPLL2_MODE
+	0x01403000, // GCC_GPLL3_MODE
+	0x01404000, // GCC_GPLL4_MODE
+	0x01405000, // GCC_GPLL5_MODE
+	0x01406000, // GCC_GPLL6_MODE
+	0x01407000, // GCC_GPLL7_MODE
+	0x01408000, // GCC_GPLL8_MODE
+	0x01409000, // GCC_GPLL9_MODE
+	0x0140a000, // GCC_GPLL10_MODE
+	0x0140b000, // GCC_GPLL11_MODE
+};
+
+static const phys_addr_t sm6115_rcg_addrs[] = {
+	0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR
+	0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
+	0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
+	0x01438028, // GCC_SDCC1_APPS_CMD_RCGR
+	0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR
+	0x0141f018, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR
+	0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
+	0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
+	0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
+	0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
+	0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
+	0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
+	0x01428014, // GCC_SLEEP_CMD_RCGR
+	0x0142802c, // GCC_XO_CMD_RCGR
+	0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR
+	0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
+	0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
+	0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
+};
+
+static const char *const sm6115_rcg_names[] = {
+	"GCC_USB30_PRIM_MASTER_CMD_RCGR",
+	"GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
+	"GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
+	"GCC_SDCC1_APPS_CMD_RCGR",
+	"GCC_SDCC2_APPS_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S0_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S1_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S2_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S3_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S4_CMD_RCGR",
+	"GCC_QUPV3_WRAP0_S5_CMD_RCGR",
+	"GCC_SLEEP_CMD_RCGR",
+	"GCC_XO_CMD_RCGR",
+	"GCC_UFS_PHY_AXI_CMD_RCGR",
+	"GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
+	"GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
+	"GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
+};
+
 static struct msm_clk_data sm6115_gcc_data = {
 	.resets = sm6115_gcc_resets,
 	.num_resets = ARRAY_SIZE(sm6115_gcc_resets),
 	.clks = sm6115_clks,
@@ -179,8 +236,14 @@  static struct msm_clk_data sm6115_gcc_data = {
 	.num_power_domains = ARRAY_SIZE(sm6115_gdscs),
 
 	.enable = sm6115_enable,
 	.set_rate = sm6115_set_rate,
+
+	.dbg_pll_addrs = sm6115_gpll_addrs,
+	.num_plls = ARRAY_SIZE(sm6115_gpll_addrs),
+	.dbg_rcg_addrs = sm6115_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sm6115_rcg_addrs),
+	.dbg_rcg_names = sm6115_rcg_names,
 };
 
 static const struct udevice_id gcc_sm6115_of_match[] = {
 	{