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[54.225.227.206]) by mx.google.com with ESMTP id o1si6294781qta.5.2016.11.14.03.34.19; Mon, 14 Nov 2016 03:34:19 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2ECCC60D88; Mon, 14 Nov 2016 11:34:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 56A66608CF; Mon, 14 Nov 2016 11:32:28 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8E2B560D5E; Mon, 14 Nov 2016 11:32:12 +0000 (UTC) Received: from mail-pg0-f49.google.com (mail-pg0-f49.google.com [74.125.83.49]) by lists.linaro.org (Postfix) with ESMTPS id 6BD2E60D56 for ; Mon, 14 Nov 2016 11:31:31 +0000 (UTC) Received: by mail-pg0-f49.google.com with SMTP id f188so53248875pgc.3 for ; Mon, 14 Nov 2016 03:31:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pEOgA70abAaZGydNQ7OFMVIYcyjlidB0lfXeEsEn2rM=; b=L9tI//akzrdhgxd/RrNX7dWjJCIkr6cnmLNbgq5+AflPgSKNy/A7FU4u3qukiG+w9K 4y9TxKJShVNu7UvVHLxVymXU6LiqSh33bf1+bsMDmsN0ZaKjQX7qXbo8nGvg+UFtiIom XfL43AKVNFCh4znY7Je93yeL8yGdDgeSk283D6Dn4gqe6J8PcmwDurJNbDeiVmLZpZN7 AMj6MwdzQmx1AduKWQgTL+PapGmLVMfofaug+vPl5qW/et78XZDFCFcPZ6S6UKkBIWBF w1gZQ8U5IE8wpqHcUgms0nOXQZcZIxSmas2AtRUyT2bugAesC+fjCbVtgUoXF2VfYdiD MPyQ== X-Gm-Message-State: ABUngvdSPplsa6fq3uZKdroMhMp8bpVuVjABNpXNsr0oQUSt2coVXBDnFgnMv5URBKkkxiQMxCM= X-Received: by 10.99.55.30 with SMTP id e30mr68510735pga.75.1479123090725; Mon, 14 Nov 2016 03:31:30 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g82sm34663209pfb.43.2016.11.14.03.31.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Nov 2016 03:31:30 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Mon, 14 Nov 2016 19:29:32 +0800 Message-Id: <1479122995-50330-6-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> References: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> Cc: Kejian Yan Subject: [Linaro-uefi] [PATCH 05/28] D02/D03/Dsdt/hns: fix the bug of serdes loopback X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The register of Hilink needs to be configed, but the current procedure does not do that. The temporary variable to be set to register is wrong, it must be Local0 instead of Local1. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan --- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 20 ++++++++++---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 12 ++++++------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index b62ee45..d8d453a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -126,16 +126,16 @@ Scope(_SB) OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) Field(H4LR, DWordAcc, NoLock, Preserve) { H4L0, 16, // port0 - H4R0, 16, //RESERVED + , 16, //RESERVED Offset (0x400), H4L1, 16, // port1 - H4R1, 16, //RESERVED + , 16, //RESERVED Offset (0x800), H4L2, 16, // port2 - H4R2, 16, //RESERVED + , 16, //RESERVED Offset (0xc00), H4L3, 16, // port3 - H4R3, 16, //RESERVED + , 16, //RESERVED } OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) Field(H3LR, DWordAcc, NoLock, Preserve) { @@ -266,42 +266,42 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L0) + Store (Local0, H4L0) } case (0x1){ Store (0, HSEL) Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L1) + Store (Local0, H4L1) } case (0x2){ Store (0, HSEL) Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L2) + Store (Local0, H4L2) } case (0x3){ Store (0, HSEL) Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L3) + Store (Local0, H4L3) } case (0x4){ Store (3, HSEL) Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L2) + Store (Local0, H3L2) } case (0x5){ Store (3, HSEL) Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L3) + Store (Local0, H3L3) } } } diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 2b08a1f..881aa14 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -250,37 +250,37 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L0) + Store (Local0, H4L0) } case (0x1){ Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L1) + Store (Local0, H4L1) } case (0x2){ Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L2) + Store (Local0, H4L2) } case (0x3){ Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L3) + Store (Local0, H4L3) } case (0x4){ Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L2) + Store (Local0, H3L2) } case (0x5){ Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L3) + Store (Local0, H3L3) } } }