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[54.225.227.206]) by mx.google.com with ESMTP id a97si14961235qkh.90.2016.11.14.03.41.49; Mon, 14 Nov 2016 03:41:49 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7B14460DA2; Mon, 14 Nov 2016 11:41:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id DCEFD60DA7; Mon, 14 Nov 2016 11:35:04 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3C4CD60D60; Mon, 14 Nov 2016 11:34:55 +0000 (UTC) Received: from mail-pg0-f45.google.com (mail-pg0-f45.google.com [74.125.83.45]) by lists.linaro.org (Postfix) with ESMTPS id 626DC60D7A for ; Mon, 14 Nov 2016 11:33:10 +0000 (UTC) Received: by mail-pg0-f45.google.com with SMTP id 3so53531435pgd.0 for ; Mon, 14 Nov 2016 03:33:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YobqFI3v/+ZkFLgt8FR19QQF2SQdYqq9GAE7rwc9dYk=; b=jJAk7sVRKSxV7z/pGpD/j6ciw/y6Mhw3heSzJo9s0eYh5ZvK9PurOpPU84uFI65Yuw Fi6hoTKzO0CzfGKcQdDqu/gbKj6cEC4yDZoA0QKF9xD+szrQmrFoVubZJE4pQk6mJ7VG /R09IHs+0k3e80hd84gj22YIUUQmbn+gd6hFkqV1AkKuKu7jmGU43rDOdA1FznjyrLBj EO3Ui+yTU0PuzBD6okPXXZbGs9NWvBT1tiNXhbmZdFJ4a22F9Y0Teyvhz5HtbPRaTUjg VrRsqAuizEgMZCD0Vox7cRyeaG/laRLBlZ4sRrEQc9RL2UusbBEED0oLbMhJsWdL/y7C NFQA== X-Gm-Message-State: ABUngvclS8c8gdBi1v66ZccmxXSLPI2FQ/GRbS+opm1rB7awbYmr4V8c4SrAO1na9FoF13QcABE= X-Received: by 10.98.18.133 with SMTP id 5mr35206030pfs.124.1479123189546; Mon, 14 Nov 2016 03:33:09 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g82sm34663209pfb.43.2016.11.14.03.32.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Nov 2016 03:33:09 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Mon, 14 Nov 2016 19:29:39 +0800 Message-Id: <1479122995-50330-13-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> References: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> Cc: Salil Mehta Subject: [Linaro-uefi] [PATCH 12/28] D03/ACPI: Add support of RoCE Reset in DSDT X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" In the Hip06 SoC, the RoCE Engine is part of the HiSilicon Network Subsystem and is dependent upon DSAF module. Therefore, certain functions like RESET are exposed through the common registers of HNS module which are memory-mapped by the HNS driver and currently can only be accessed through DT/syscon interface. This patch adds the support of the RoCE Reset functionality through ACPI interface. This functionality would be exposed to the HiSilicon HNS Driver using the _DSM() ACPI Method. This method shall be called by the wrapper API in HNS driver. Further, HiSilicon RoCE driver shall call the HNS Driver exported RoCE Reset API. In this patch, DSDT ACPI Table have been amended to facilitate such support. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 79 +++++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 83cea5e..192e76d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -115,6 +115,33 @@ Scope(_SB) , 31, //RESERVED } + // DSAF Channel RESET + OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8) + Field(DCRR, DWordAcc, NoLock, Preserve) { + DCRE, 1, + , 31, //RESERVED + DCRD, 1, + , 31, //RESERVED + } + + // RoCE RESET + OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8) + Field(RKRR, DWordAcc, NoLock, Preserve) { + RKRE, 1, + , 31, //RESERVED + RKRD, 1, + , 31, //RESERVED + } + + // RoCE Clock enable/disable + OperationRegion(RKCR, SystemMemory, 0xC0000328, 8) + Field(RKCR, DWordAcc, NoLock, Preserve) { + RCLE, 1, + , 31, //RESERVED + RCLD, 1, + , 31, //RESERVED + } + // Hilink access sel cfg reg OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) Field(HSER, DWordAcc, NoLock, Preserve) { @@ -254,6 +281,30 @@ Scope(_SB) } } + //reset DSAF channels + //Arg0 : mask + //Arg1 : 0 reset, 1 de-reset + Method(DCRT, 2, Serialized) { + If (LEqual (Arg1, 0)) { + Store(Arg0, DCRE) + } Else { + Store(Arg0, DCRD) + } + } + + //reset RoCE + //Arg0 : 0 reset, 1 de-reset + Method(RRST, 1, Serialized) { + If (LEqual (Arg0, 0)) { + Store(0x1, RKRE) + } Else { + Store(0x1, RCLD) + Store(0x1, RKRD) + sleep(20) + Store(0x1, RCLE) + } + } + // Set Serdes Loopback //Arg0 : port //Arg1 : 0 disable, 1 enable @@ -307,7 +358,7 @@ Scope(_SB) } //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg0 : reset type (1: dsaf; 2: ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) //Arg1 : port //Arg2 : 0 disable, 1 enable Method(DRST, 3, Serialized) @@ -363,6 +414,22 @@ Scope(_SB) Store (Arg2, Local1) GRST (Local0, Local1) } + + //Reset DSAF Channels + case (0x6) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + DCRT (Local0, Local1) + } + + //Reset RoCE + case (0x7) + { + // Discarding Arg1 as it is always 0 + Store (Arg2, Local0) + RRST (Local0) + } } } @@ -373,7 +440,7 @@ Scope(_SB) // Arg2: Integer Function Index // 0 : Return Supported Functions bit mask // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) // Arg3[1] : port index in dsaf // Arg3[2] : 0 reset, 1 cancle reset // 2 : Set Serdes Loopback @@ -612,5 +679,13 @@ Scope(_SB) 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, } }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) } }