| Message ID | 20240822152801.602318-9-claudiu.beznea.uj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add initial USB support for the Renesas RZ/G3S SoC | expand |
Hi Claudiu, > -----Original Message----- > From: Claudiu <claudiu.beznea@tuxon.dev> > Sent: Thursday, August 22, 2024 4:28 PM > Subject: [PATCH 08/16] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S > > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add support for RZ/G3S SoC. It needs its own compatible as it uses 2 reset signals and it cannot work > w/o both of them. To be able to fully validate this on DT schema, too, the RZ/G3S uses it's own > compatible w/o a fallback (as if the fallback will be used the RZ/G3S will not work anyway). Other than reset/ power domain approach for handling USBPWRRDY signal Can't USBPWRRDY signal handled in SYSC driver directly? Since SYSC driver init happens at very early boot stage Check for USBPHY control device availability and handle USBPWRRDY signal there?? Cheers, Biju > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > drivers/reset/reset-rzg2l-usbphy-ctrl.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c > index 8b64c12f3bec..08b18d7de7ad 100644 > --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c > +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c > @@ -93,6 +93,7 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev, > > static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { > { .compatible = "renesas,rzg2l-usbphy-ctrl" }, > + { .compatible = "renesas,r9a08g045-usbphy-ctrl" }, > { /* Sentinel */ } > }; > MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); > -- > 2.39.2
Hi Claudiu, > -----Original Message----- > From: claudiu beznea <claudiu.beznea@tuxon.dev> > Sent: Friday, August 23, 2024 9:41 AM > Subject: Re: [PATCH 08/16] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S > > Hi, Biju, > > On 22.08.2024 19:59, Biju Das wrote: > > Hi Claudiu, > > > >> -----Original Message----- > >> From: Claudiu <claudiu.beznea@tuxon.dev> > >> Sent: Thursday, August 22, 2024 4:28 PM > >> Subject: [PATCH 08/16] reset: rzg2l-usbphy-ctrl: Add support for > >> RZ/G3S > >> > >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >> > >> Add support for RZ/G3S SoC. It needs its own compatible as it uses 2 > >> reset signals and it cannot work w/o both of them. To be able to > >> fully validate this on DT schema, too, the RZ/G3S uses it's own compatible w/o a fallback (as if > the fallback will be used the RZ/G3S will not work anyway). > > > > Other than reset/ power domain approach for handling USBPWRRDY signal > > > > Can't USBPWRRDY signal handled in SYSC driver directly? Since SYSC > > driver init happens at very early boot stage Check for USBPHY control device availability and handle > USBPWRRDY signal there?? > > In theory, it can be done this way, too. The downside I see at the moment with this approach would be > that the USB, PCIe drivers will not be in charge with handling their signals, there will be no direct > dependency available b/w SYSC and USB drivers. SYSC driver probe/init will happen before USB driver because of early init calls. So, I don't think there will be a problem. Cheers, Biju > >> > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >> --- > >> drivers/reset/reset-rzg2l-usbphy-ctrl.c | 1 + > >> 1 file changed, 1 insertion(+) > >> > >> diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c > >> b/drivers/reset/reset-rzg2l-usbphy-ctrl.c > >> index 8b64c12f3bec..08b18d7de7ad 100644 > >> --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c > >> +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c > >> @@ -93,6 +93,7 @@ static int rzg2l_usbphy_ctrl_status(struct > >> reset_controller_dev *rcdev, > >> > >> static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { > >> { .compatible = "renesas,rzg2l-usbphy-ctrl" }, > >> + { .compatible = "renesas,r9a08g045-usbphy-ctrl" }, > >> { /* Sentinel */ } > >> }; > >> MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); > >> -- > >> 2.39.2 > >
On Thu, Aug 22, 2024 at 5:28 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add support for RZ/G3S SoC. It needs its own compatible as it uses 2 > reset signals and it cannot work w/o both of them. To be able to > fully validate this on DT schema, too, the RZ/G3S uses it's own compatible its > w/o a fallback (as if the fallback will be used the RZ/G3S will not work > anyway). > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c index 8b64c12f3bec..08b18d7de7ad 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -93,6 +93,7 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev, static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { { .compatible = "renesas,rzg2l-usbphy-ctrl" }, + { .compatible = "renesas,r9a08g045-usbphy-ctrl" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);