Message ID | 20240913083724.1217691-3-quic_qianyu@quicinc.com |
---|---|
State | New |
Headers | show |
Series | Add support for PCIe3 on x1e80100 | expand |
On Fri, Sep 13, 2024 at 01:37:21AM -0700, Qiang Yu wrote: > Add OPP table so that PCIe is able to adjust power domain performance > state and ICC peak bw according to PCIe gen speed and link width. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index a9db0a231563..e2d6719ca54d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -70,6 +70,10 @@ properties: - const: pci # PCIe core reset - const: link_down # PCIe link down reset + operating-points-v2: true + opp-table: + type: object + allOf: - $ref: qcom,pcie-common.yaml#
Add OPP table so that PCIe is able to adjust power domain performance state and ICC peak bw according to PCIe gen speed and link width. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ 1 file changed, 4 insertions(+)