| Message ID | 20240927142108.1156362-3-dave.jiang@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | acpi/hmat / cxl: Add exclusive caching enumeration and RAS support | expand |
On Fri, 27 Sep 2024 07:16:54 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Store the address mode as part of the cache attriutes. Export the mode > attribute to sysfs as all other cache attributes. > > Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ > Signed-off-by: Dave Jiang <dave.jiang@intel.com> Minor things inline. Basically looks fine. Jonathan > --- > Documentation/ABI/stable/sysfs-devices-node | 7 +++++++ > drivers/acpi/numa/hmat.c | 3 +++ > drivers/base/node.c | 2 ++ > include/linux/node.h | 7 +++++++ > 4 files changed, 19 insertions(+) > > diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node > index 402af4b2b905..9016cc4f027c 100644 > --- a/Documentation/ABI/stable/sysfs-devices-node > +++ b/Documentation/ABI/stable/sysfs-devices-node > @@ -177,6 +177,13 @@ Description: > The cache write policy: 0 for write-back, 1 for write-through, > other or unknown. > > +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/mode > +Date: September 2024 > +Contact: Dave Jiang <dave.jiang@intel.com> > +Description: > + The address mode: 0 for reserved, 1 for extended-lniear, linear also, is 0 reserved or unknown? I'm confused. > + other unknown. > + > What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes > Date: November 2021 > Contact: Jarkko Sakkinen <jarkko@kernel.org> > diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c > index 1a902a02390f..39524f36be5b 100644 > --- a/drivers/acpi/numa/hmat.c > +++ b/drivers/acpi/numa/hmat.c > @@ -506,6 +506,9 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, > switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) { > case ACPI_HMAT_CA_DIRECT_MAPPED: > tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP; > + /* Extended Linear mode is only valid if cache is direct mapped */ > + if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) > + tcache->cache_attrs.mode = NODE_CACHE_MODE_EXTENDED_LINEAR; > break; > case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING: > tcache->cache_attrs.indexing = NODE_CACHE_INDEXED; > diff --git a/drivers/base/node.c b/drivers/base/node.c > index eb72580288e6..744be5470728 100644 > --- a/drivers/base/node.c > +++ b/drivers/base/node.c > @@ -244,12 +244,14 @@ CACHE_ATTR(size, "%llu") > CACHE_ATTR(line_size, "%u") > CACHE_ATTR(indexing, "%u") > CACHE_ATTR(write_policy, "%u") > +CACHE_ATTR(mode, "%u") > > static struct attribute *cache_attrs[] = { > &dev_attr_indexing.attr, > &dev_attr_size.attr, > &dev_attr_line_size.attr, > &dev_attr_write_policy.attr, > + &dev_attr_mode.attr, > NULL, > }; > ATTRIBUTE_GROUPS(cache); > diff --git a/include/linux/node.h b/include/linux/node.h > index 9a881c2208b3..589951c5e36f 100644 > --- a/include/linux/node.h > +++ b/include/linux/node.h > @@ -57,6 +57,11 @@ enum cache_write_policy { > NODE_CACHE_WRITE_OTHER, > }; > > +enum cache_mode { > + NODE_CACHE_MODE_UNKOWN, UNKNOWN > + NODE_CACHE_MODE_EXTENDED_LINEAR, > +}; > + > /** > * struct node_cache_attrs - system memory caching attributes > * > @@ -65,6 +70,7 @@ enum cache_write_policy { > * @size: Total size of cache in bytes > * @line_size: Number of bytes fetched on a cache miss > * @level: The cache hierarchy level > + * @mode: The address mode > */ > struct node_cache_attrs { > enum cache_indexing indexing; > @@ -72,6 +78,7 @@ struct node_cache_attrs { > u64 size; > u16 line_size; > u8 level; > + u16 mode; > }; > > #ifdef CONFIG_HMEM_REPORTING
diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node index 402af4b2b905..9016cc4f027c 100644 --- a/Documentation/ABI/stable/sysfs-devices-node +++ b/Documentation/ABI/stable/sysfs-devices-node @@ -177,6 +177,13 @@ Description: The cache write policy: 0 for write-back, 1 for write-through, other or unknown. +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/mode +Date: September 2024 +Contact: Dave Jiang <dave.jiang@intel.com> +Description: + The address mode: 0 for reserved, 1 for extended-lniear, + other unknown. + What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes Date: November 2021 Contact: Jarkko Sakkinen <jarkko@kernel.org> diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index 1a902a02390f..39524f36be5b 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -506,6 +506,9 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) { case ACPI_HMAT_CA_DIRECT_MAPPED: tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP; + /* Extended Linear mode is only valid if cache is direct mapped */ + if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) + tcache->cache_attrs.mode = NODE_CACHE_MODE_EXTENDED_LINEAR; break; case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING: tcache->cache_attrs.indexing = NODE_CACHE_INDEXED; diff --git a/drivers/base/node.c b/drivers/base/node.c index eb72580288e6..744be5470728 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -244,12 +244,14 @@ CACHE_ATTR(size, "%llu") CACHE_ATTR(line_size, "%u") CACHE_ATTR(indexing, "%u") CACHE_ATTR(write_policy, "%u") +CACHE_ATTR(mode, "%u") static struct attribute *cache_attrs[] = { &dev_attr_indexing.attr, &dev_attr_size.attr, &dev_attr_line_size.attr, &dev_attr_write_policy.attr, + &dev_attr_mode.attr, NULL, }; ATTRIBUTE_GROUPS(cache); diff --git a/include/linux/node.h b/include/linux/node.h index 9a881c2208b3..589951c5e36f 100644 --- a/include/linux/node.h +++ b/include/linux/node.h @@ -57,6 +57,11 @@ enum cache_write_policy { NODE_CACHE_WRITE_OTHER, }; +enum cache_mode { + NODE_CACHE_MODE_UNKOWN, + NODE_CACHE_MODE_EXTENDED_LINEAR, +}; + /** * struct node_cache_attrs - system memory caching attributes * @@ -65,6 +70,7 @@ enum cache_write_policy { * @size: Total size of cache in bytes * @line_size: Number of bytes fetched on a cache miss * @level: The cache hierarchy level + * @mode: The address mode */ struct node_cache_attrs { enum cache_indexing indexing; @@ -72,6 +78,7 @@ struct node_cache_attrs { u64 size; u16 line_size; u8 level; + u16 mode; }; #ifdef CONFIG_HMEM_REPORTING
Store the address mode as part of the cache attriutes. Export the mode attribute to sysfs as all other cache attributes. Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- Documentation/ABI/stable/sysfs-devices-node | 7 +++++++ drivers/acpi/numa/hmat.c | 3 +++ drivers/base/node.c | 2 ++ include/linux/node.h | 7 +++++++ 4 files changed, 19 insertions(+)