@@ -4819,6 +4819,7 @@ static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry_outer = 3;
int retry_inner;
+ int ret;
start:
if (ufshcd_is_hba_active(hba))
@@ -4865,6 +4866,22 @@ static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
/* enable UIC related interrupts */
ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ /*
+ * Do dme_reset and dme_enable if a UFS host controller need
+ * this procedure to actually finish HCE.
+ */
+ if (hba->quirks & UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE) {
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (ret)
+ dev_err(hba->dev,
+ "Failed to do dme_enable after HCE.\n");
+ } else {
+ dev_err(hba->dev, "Failed to do dme_reset after HCE.\n");
+ }
+ }
+
ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
return 0;
@@ -685,6 +685,12 @@ enum ufshcd_quirks {
* single doorbell mode.
*/
UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
+
+ /*
+ * This quirks needs to be enabled if host controller need to
+ * do dme_reset and dme_enable after hce.
+ */
+ UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE = 1 << 26,
};
enum ufshcd_caps {
HCE on Rockchip SoC is different from both of ufshcd_hba_execute_hce() and UFSHCI_QUIRK_BROKEN_HCE case. It need to do dme_reset and dme_enable after enabling HCE. So in order not to abuse UFSHCI_QUIRK_BROKEN_HCE, add a new quirk UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE, to deal with that limitation. Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v3: None Changes in v2: None drivers/ufs/core/ufshcd.c | 17 +++++++++++++++++ include/ufs/ufshcd.h | 6 ++++++ 2 files changed, 23 insertions(+)