| Message ID | 20241014-x1e80100-qcp-sdhc-v2-2-868e70a825e0@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Describe SDCs and enable support on QCP | expand |
On 14.10.2024 10:19 AM, Abel Vesa wrote: > Describe the SDC2 default and sleep state pins configuration > in TLMM. Do this in SoC dtsi file since they will be shared > across multiple boards. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 40 ++++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 2d0befd6ba0ea11fdf2305d23c0cd8743de303dc..dfdae4f9225740bb3d2de6b0054ed60a2397bba9 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -5741,6 +5741,46 @@ rx-pins { > bias-disable; > }; > }; > + > + sdc2_sleep: sdc2-sleep-state { > + clk-pins { > + pins = "sdc2_clk"; > + bias-disable; > + drive-strength = <2>; Other nodes have bias after drive-strength Also unusual to have _sleep before _default The nodes look sane otherwise Konrad
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 2d0befd6ba0ea11fdf2305d23c0cd8743de303dc..dfdae4f9225740bb3d2de6b0054ed60a2397bba9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5741,6 +5741,46 @@ rx-pins { bias-disable; }; }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; }; apps_smmu: iommu@15000000 {
Describe the SDC2 default and sleep state pins configuration in TLMM. Do this in SoC dtsi file since they will be shared across multiple boards. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)