| Message ID | 20241016202814.4061541-10-samuel.holland@sifive.com |
|---|---|
| State | Accepted |
| Commit | 1851e7836212c76bebb6944bb1541ddcccbea535 |
| Headers | show |
| Series | riscv: Userspace pointer masking and tagged address ABI | expand |
On Thu, Oct 17, 2024 at 1:58 AM Samuel Holland <samuel.holland@sifive.com> wrote: > > The interface for controlling pointer masking in VS-mode is henvcfg.PMM, > which is part of the Ssnpm extension, even though pointer masking in > HS-mode is provided by the Smnpm extension. As a result, emulating Smnpm > in the guest requires (only) Ssnpm on the host. > > The guest configures Smnpm through the SBI Firmware Features extension, > which KVM does not yet implement, so currently the ISA extension has no > visible effect on the guest, and thus it cannot be disabled. Ssnpm is > configured using the senvcfg CSR within the guest, so that extension > cannot be hidden from the guest without intercepting writes to the CSR. > > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > > Changes in v5: > - Do not allow Smnpm to be disabled, as suggested by Anup > > Changes in v2: > - New patch for v2 > > arch/riscv/include/uapi/asm/kvm.h | 2 ++ > arch/riscv/kvm/vcpu_onereg.c | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index e97db3296456..4f24201376b1 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZCF, > KVM_RISCV_ISA_EXT_ZCMOP, > KVM_RISCV_ISA_EXT_ZAWRS, > + KVM_RISCV_ISA_EXT_SMNPM, > + KVM_RISCV_ISA_EXT_SSNPM, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index b319c4c13c54..5b68490ad9b7 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -34,9 +34,11 @@ static const unsigned long kvm_isa_ext_arr[] = { > [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, > [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, > /* Multi letter extensions (alphabetically sorted) */ > + [KVM_RISCV_ISA_EXT_SMNPM] = RISCV_ISA_EXT_SSNPM, > KVM_ISA_EXT_ARR(SMSTATEEN), > KVM_ISA_EXT_ARR(SSAIA), > KVM_ISA_EXT_ARR(SSCOFPMF), > + KVM_ISA_EXT_ARR(SSNPM), > KVM_ISA_EXT_ARR(SSTC), > KVM_ISA_EXT_ARR(SVINVAL), > KVM_ISA_EXT_ARR(SVNAPOT), > @@ -127,8 +129,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_C: > case KVM_RISCV_ISA_EXT_I: > case KVM_RISCV_ISA_EXT_M: > + case KVM_RISCV_ISA_EXT_SMNPM: > /* There is not architectural config bit to disable sscofpmf completely */ > case KVM_RISCV_ISA_EXT_SSCOFPMF: > + case KVM_RISCV_ISA_EXT_SSNPM: > case KVM_RISCV_ISA_EXT_SSTC: > case KVM_RISCV_ISA_EXT_SVINVAL: > case KVM_RISCV_ISA_EXT_SVNAPOT: > -- > 2.45.1 >
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index e97db3296456..4f24201376b1 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCF, KVM_RISCV_ISA_EXT_ZCMOP, KVM_RISCV_ISA_EXT_ZAWRS, + KVM_RISCV_ISA_EXT_SMNPM, + KVM_RISCV_ISA_EXT_SSNPM, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index b319c4c13c54..5b68490ad9b7 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -34,9 +34,11 @@ static const unsigned long kvm_isa_ext_arr[] = { [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, /* Multi letter extensions (alphabetically sorted) */ + [KVM_RISCV_ISA_EXT_SMNPM] = RISCV_ISA_EXT_SSNPM, KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), + KVM_ISA_EXT_ARR(SSNPM), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -127,8 +129,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_C: case KVM_RISCV_ISA_EXT_I: case KVM_RISCV_ISA_EXT_M: + case KVM_RISCV_ISA_EXT_SMNPM: /* There is not architectural config bit to disable sscofpmf completely */ case KVM_RISCV_ISA_EXT_SSCOFPMF: + case KVM_RISCV_ISA_EXT_SSNPM: case KVM_RISCV_ISA_EXT_SSTC: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT:
The interface for controlling pointer masking in VS-mode is henvcfg.PMM, which is part of the Ssnpm extension, even though pointer masking in HS-mode is provided by the Smnpm extension. As a result, emulating Smnpm in the guest requires (only) Ssnpm on the host. The guest configures Smnpm through the SBI Firmware Features extension, which KVM does not yet implement, so currently the ISA extension has no visible effect on the guest, and thus it cannot be disabled. Ssnpm is configured using the senvcfg CSR within the guest, so that extension cannot be hidden from the guest without intercepting writes to the CSR. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v5: - Do not allow Smnpm to be disabled, as suggested by Anup Changes in v2: - New patch for v2 arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu_onereg.c | 4 ++++ 2 files changed, 6 insertions(+)