| Message ID | 20241021145832.34920-1-philmd@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/mips: Introduce ase_3d_available() helper | expand |
On 21/10/24 11:58, Philippe Mathieu-Daudé wrote: > Determine if the MIPS-3D ASE is implemented by checking > the state of the 3D bit in the FIR CP1 control register. > Remove the then unused ASE_MIPS3D definition. I forgot to mention: "Note, this allows using MIPS-3D on the 20Kc model." > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/mips/cpu.h | 6 ++++++ > target/mips/mips-defs.h | 1 - > target/mips/tcg/translate.c | 8 ++++++-- > target/mips/cpu-defs.c.inc | 4 ++-- > target/mips/tcg/micromips_translate.c.inc | 5 ++++- > 5 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index a4a46ebbe98..6a4c4ea683a 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -1319,6 +1319,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); > bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); > bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); > > +/* Check presence of MIPS-3D ASE */ > +static inline bool ase_3d_available(CPUMIPSState *env) > +{ > + return env->active_fpu.fcr0 & (1 << FCR0_3D); > +} > + > /* Check presence of MSA implementation */ > static inline bool ase_msa_available(CPUMIPSState *env) > { > diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h > index a6cebe0265c..6b5cd0d8f53 100644 > --- a/target/mips/mips-defs.h > +++ b/target/mips/mips-defs.h > @@ -26,7 +26,6 @@ > * bits 24-39: MIPS ASEs > */ > #define ASE_MIPS16 0x0000000001000000ULL > -#define ASE_MIPS3D 0x0000000002000000ULL > #define ASE_MDMX 0x0000000004000000ULL > #define ASE_DSP 0x0000000008000000ULL > #define ASE_DSP_R2 0x0000000010000000ULL > diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c > index d92fc418edd..9e0c319bb23 100644 > --- a/target/mips/tcg/translate.c > +++ b/target/mips/tcg/translate.c > @@ -14952,7 +14952,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) > } else { > /* OPC_BC1ANY2 */ > check_cop1x(ctx); > - check_insn(ctx, ASE_MIPS3D); > + if (!ase_3d_available(env)) { > + return false; > + } > gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), > (rt >> 2) & 0x7, imm << 2); > } > @@ -14967,7 +14969,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) > check_cp1_enabled(ctx); > check_insn_opc_removed(ctx, ISA_MIPS_R6); > check_cop1x(ctx); > - check_insn(ctx, ASE_MIPS3D); > + if (!ase_3d_available(env)) { > + return false; > + } > /* fall through */ > case OPC_BC1: > check_cp1_enabled(ctx); > diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc > index 19e2abac829..2728f4dba67 100644 > --- a/target/mips/cpu-defs.c.inc > +++ b/target/mips/cpu-defs.c.inc > @@ -663,7 +663,7 @@ const mips_def_t mips_defs[] = > .CP1_fcr31_rw_bitmask = 0xFF83FFFF, > .SEGBITS = 40, > .PABITS = 36, > - .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D, > + .insn_flags = CPU_MIPS64R1, > .mmu_type = MMU_TYPE_R4000, > }, > { > @@ -692,7 +692,7 @@ const mips_def_t mips_defs[] = > .CP1_fcr31_rw_bitmask = 0xFF83FFFF, > .SEGBITS = 42, > .PABITS = 36, > - .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, > + .insn_flags = CPU_MIPS64R2, > .mmu_type = MMU_TYPE_R4000, > }, > { > diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc > index 3cbf53bf2b3..c479bec1081 100644 > --- a/target/mips/tcg/micromips_translate.c.inc > +++ b/target/mips/tcg/micromips_translate.c.inc > @@ -2484,7 +2484,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) > mips32_op = OPC_BC1TANY4; > do_cp1mips3d: > check_cop1x(ctx); > - check_insn(ctx, ASE_MIPS3D); > + if (!ase_3d_available(env)) { > + gen_reserved_instruction(ctx); > + break; > + } > /* Fall through */ > do_cp1branch: > if (env->CP0_Config1 & (1 << CP0C1_FP)) {
On 10/21/24 08:02, Philippe Mathieu-Daudé wrote: > On 21/10/24 11:58, Philippe Mathieu-Daudé wrote: >> Determine if the MIPS-3D ASE is implemented by checking >> the state of the 3D bit in the FIR CP1 control register. >> Remove the then unused ASE_MIPS3D definition. > > I forgot to mention: > > "Note, this allows using MIPS-3D on the 20Kc model." Did you mean mips64dspr2? The 20Kc model has ASE_MIPS3D. If so, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 21/10/24 14:24, Richard Henderson wrote: > On 10/21/24 08:02, Philippe Mathieu-Daudé wrote: >> On 21/10/24 11:58, Philippe Mathieu-Daudé wrote: >>> Determine if the MIPS-3D ASE is implemented by checking >>> the state of the 3D bit in the FIR CP1 control register. >>> Remove the then unused ASE_MIPS3D definition. >> >> I forgot to mention: >> >> "Note, this allows using MIPS-3D on the 20Kc model." > > Did you mean mips64dspr2? Yes... Nice catch. > The 20Kc model has ASE_MIPS3D. > > If so, > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Thanks!
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a4a46ebbe98..6a4c4ea683a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1319,6 +1319,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); +/* Check presence of MIPS-3D ASE */ +static inline bool ase_3d_available(CPUMIPSState *env) +{ + return env->active_fpu.fcr0 & (1 << FCR0_3D); +} + /* Check presence of MSA implementation */ static inline bool ase_msa_available(CPUMIPSState *env) { diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index a6cebe0265c..6b5cd0d8f53 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -26,7 +26,6 @@ * bits 24-39: MIPS ASEs */ #define ASE_MIPS16 0x0000000001000000ULL -#define ASE_MIPS3D 0x0000000002000000ULL #define ASE_MDMX 0x0000000004000000ULL #define ASE_DSP 0x0000000008000000ULL #define ASE_DSP_R2 0x0000000010000000ULL diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index d92fc418edd..9e0c319bb23 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -14952,7 +14952,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) } else { /* OPC_BC1ANY2 */ check_cop1x(ctx); - check_insn(ctx, ASE_MIPS3D); + if (!ase_3d_available(env)) { + return false; + } gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); } @@ -14967,7 +14969,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) check_cp1_enabled(ctx); check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cop1x(ctx); - check_insn(ctx, ASE_MIPS3D); + if (!ase_3d_available(env)) { + return false; + } /* fall through */ case OPC_BC1: check_cp1_enabled(ctx); diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 19e2abac829..2728f4dba67 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -663,7 +663,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 36, - .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D, + .insn_flags = CPU_MIPS64R1, .mmu_type = MMU_TYPE_R4000, }, { @@ -692,7 +692,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 42, .PABITS = 36, - .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, + .insn_flags = CPU_MIPS64R2, .mmu_type = MMU_TYPE_R4000, }, { diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 3cbf53bf2b3..c479bec1081 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -2484,7 +2484,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); - check_insn(ctx, ASE_MIPS3D); + if (!ase_3d_available(env)) { + gen_reserved_instruction(ctx); + break; + } /* Fall through */ do_cp1branch: if (env->CP0_Config1 & (1 << CP0C1_FP)) {
Determine if the MIPS-3D ASE is implemented by checking the state of the 3D bit in the FIR CP1 control register. Remove the then unused ASE_MIPS3D definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/mips/cpu.h | 6 ++++++ target/mips/mips-defs.h | 1 - target/mips/tcg/translate.c | 8 ++++++-- target/mips/cpu-defs.c.inc | 4 ++-- target/mips/tcg/micromips_translate.c.inc | 5 ++++- 5 files changed, 18 insertions(+), 6 deletions(-)