Message ID | 20241028-upstream_s32cc_gmac-v4-16-03618f10e3e2@oss.nxp.com |
---|---|
State | New |
Headers | show |
Series | Add support for Synopsis DWMAC IP on NXP Automotive SoCs S32G2xx/S32G3xx/S32R45 | expand |
On Mon, Oct 28, 2024 at 09:24:58PM +0100, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > The PTP clock is read by stmmac_platform during DT parse. > On S32G/R the clock is not ready and returns 0. Postpone > reading of the clock on PTP init. This needs more explanation as to why this is a feature, not a bug, for the PTP clock. Andrew
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c index fba221c37594..da2cdcfd0529 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -140,6 +140,18 @@ static void s32_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) dev_err(gmac->dev, "Can't set tx clock\n"); } +static void s32_dwmac_ptp_clk_freq_config(struct stmmac_priv *priv) +{ + struct plat_stmmacenet_data *plat = priv->plat; + + if (!plat->clk_ptp_ref) + return; + + plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref); + + netdev_dbg(priv->dev, "PTP rate %lu\n", plat->clk_ptp_rate); +} + static int s32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat; @@ -195,6 +207,7 @@ static int s32_dwmac_probe(struct platform_device *pdev) plat->init = s32_gmac_init; plat->exit = s32_gmac_exit; plat->fix_mac_speed = s32_fix_mac_speed; + plat->ptp_clk_freq_config = s32_dwmac_ptp_clk_freq_config; plat->bsp_priv = gmac;