From patchwork Thu Nov 24 15:14:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 83922 Delivered-To: patch@linaro.org Received: by 10.182.1.168 with SMTP id 8csp213236obn; Thu, 24 Nov 2016 07:16:53 -0800 (PST) X-Received: by 10.84.210.73 with SMTP id z67mr6536930plh.112.1480000613526; Thu, 24 Nov 2016 07:16:53 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 30si39866307pgx.304.2016.11.24.07.16.52; Thu, 24 Nov 2016 07:16:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966518AbcKXPQK (ORCPT + 25 others); Thu, 24 Nov 2016 10:16:10 -0500 Received: from mail-wm0-f49.google.com ([74.125.82.49]:38296 "EHLO mail-wm0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966112AbcKXPPh (ORCPT ); Thu, 24 Nov 2016 10:15:37 -0500 Received: by mail-wm0-f49.google.com with SMTP id f82so64805338wmf.1 for ; Thu, 24 Nov 2016 07:14:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DiGMkSPHu/wZ8P0f0MGeDREeuwIm+KQlVTkIhitNN+c=; b=M6QPvNlP/DSM02iZs0fjyVb6//IHKLS8cZO95ywUJGAoHkE7j7eEIwdTy0RCFGL69I Kon37OIML39tZOG8EZXRfELmkRGPxyVSCW5n2plMFZHk1sy+cZI/OGV7FncJm8BuJ2aW HtVac3Wh5AspQhicUnj1T1z+fGdXRbwGK2OrY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DiGMkSPHu/wZ8P0f0MGeDREeuwIm+KQlVTkIhitNN+c=; b=PFJOznUNagxuuy9Vt+GRLag6oaKM0X94S0v8aFL3ZSYkjAvM3E7cZGWkg1xKaaB3ys 7w44NYTXV0bT80aCIrp0mkdsq7Vl/OLqNBLCayNbjnq8hXh9Y837XaidtyapGEsdR1hq w973qX3o/nKBtNDmUcmeY3qN8Pw9Fqrtr7KFDbNXc5DDl+71f+K9NuDJZ3q+PBtRWEGW lEH0f3UyMPzJIYJXzcxxIVEMTY0koC5HTCT2BhkZwIruiU8wVZWWwRZcwSmpIm/M5LLN 6rYkltny9eAaBQfVdH6rgWIKXXwD4vaL1Doc49AaWP9LCBMxA00OMODJvNL6apnnS358 ZQ1A== X-Gm-Message-State: AKaTC038h/ZYDwXp5JiIJAEtRaWHqHomas6JcxiQGwBsDjvjd2fZ6uTZalCj0fRwnz+ZpnMr X-Received: by 10.194.222.202 with SMTP id qo10mr2717885wjc.115.1480000493543; Thu, 24 Nov 2016 07:14:53 -0800 (PST) Received: from lmenx321.st.com. ([80.215.203.217]) by smtp.gmail.com with ESMTPSA id ct7sm24062084wjc.2.2016.11.24.07.14.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Nov 2016 07:14:53 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v2 4/7] PWM: add pwm driver for stm32 plaftorm Date: Thu, 24 Nov 2016 16:14:20 +0100 Message-Id: <1480000463-9625-5-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480000463-9625-1-git-send-email-benjamin.gaignard@st.com> References: <1480000463-9625-1-git-send-email-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver add support for pwm driver on stm32 platform. The SoC have multiple instances of the hardware IP and each of them could have small differences: number of channels, complementary output, counter register size... Use DT parameters to handle those differentes configuration version 2: - only keep one comptatible - use DT paramaters to discover hardware block configuration Signed-off-by: Benjamin Gaignard --- drivers/pwm/Kconfig | 8 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 285 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 294 insertions(+) create mode 100644 drivers/pwm/pwm-stm32.c -- 1.9.1 diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index bf01288..a89fdba 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -388,6 +388,14 @@ config PWM_STI To compile this driver as a module, choose M here: the module will be called pwm-sti. +config PWM_STM32 + bool "STMicroelectronics STM32 PWM" + depends on ARCH_STM32 + depends on OF + select MFD_STM32_GP_TIMER + help + Generic PWM framework driver for STM32 SoCs. + config PWM_STMPE bool "STMPE expander PWM export" depends on MFD_STMPE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 1194c54..5aa9308 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_STI) += pwm-sti.o +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c new file mode 100644 index 0000000..a362f63 --- /dev/null +++ b/drivers/pwm/pwm-stm32.c @@ -0,0 +1,285 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * Author: Gerald Baeza + * License terms: GNU General Public License (GPL), version 2 + * + * Inspired by timer-stm32.c from Maxime Coquelin + * pwm-atmel.c from Bo Shen + */ + +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "stm32-pwm" + +#define CAP_COMPLEMENTARY BIT(0) +#define CAP_32BITS_COUNTER BIT(1) +#define CAP_BREAKINPUT BIT(2) +#define CAP_BREAKINPUT_POLARITY BIT(3) + +struct stm32_pwm_dev { + struct device *dev; + struct clk *clk; + struct regmap *regmap; + struct pwm_chip chip; + int caps; + int npwm; + u32 polarity; +}; + +#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip) + +static u32 __active_channels(struct stm32_pwm_dev *pwm_dev) +{ + u32 ccer; + + regmap_read(pwm_dev->regmap, TIM_CCER, &ccer); + + return ccer & TIM_CCER_CCXE; +} + +static int write_ccrx(struct stm32_pwm_dev *dev, struct pwm_device *pwm, + u32 ccr) +{ + switch (pwm->hwpwm) { + case 0: + return regmap_write(dev->regmap, TIM_CCR1, ccr); + case 1: + return regmap_write(dev->regmap, TIM_CCR2, ccr); + case 2: + return regmap_write(dev->regmap, TIM_CCR3, ccr); + case 3: + return regmap_write(dev->regmap, TIM_CCR4, ccr); + } + return -EINVAL; +} + +static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip); + unsigned long long prd, div, dty; + int prescaler = 0; + u32 max_arr = 0xFFFF, ccmr, mask, shift, bdtr; + + if (dev->caps & CAP_32BITS_COUNTER) + max_arr = 0xFFFFFFFF; + + /* Period and prescaler values depends of clock rate */ + div = (unsigned long long)clk_get_rate(dev->clk) * period_ns; + + do_div(div, NSEC_PER_SEC); + prd = div; + + while (div > max_arr) { + prescaler++; + div = prd; + do_div(div, (prescaler + 1)); + } + prd = div; + + if (prescaler > MAX_TIM_PSC) { + dev_err(chip->dev, "prescaler exceeds the maximum value\n"); + return -EINVAL; + } + + /* All channels share the same prescaler and counter so + * when two channels are active at the same we can't change them + */ + if (__active_channels(dev) & ~(1 << pwm->hwpwm * 4)) { + u32 psc, arr; + + regmap_read(dev->regmap, TIM_PSC, &psc); + regmap_read(dev->regmap, TIM_ARR, &arr); + + if ((psc != prescaler) || (arr != prd - 1)) + return -EINVAL; + } + + regmap_write(dev->regmap, TIM_PSC, prescaler); + regmap_write(dev->regmap, TIM_ARR, prd - 1); + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); + + /* Calculate the duty cycles */ + dty = prd * duty_ns; + do_div(dty, period_ns); + + write_ccrx(dev, pwm, dty); + + /* Configure output mode */ + shift = (pwm->hwpwm & 0x1) * 8; + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; + mask = 0xFF << shift; + + if (pwm->hwpwm & 0x2) + regmap_update_bits(dev->regmap, TIM_CCMR2, mask, ccmr); + else + regmap_update_bits(dev->regmap, TIM_CCMR1, mask, ccmr); + + if (!(dev->caps & CAP_BREAKINPUT)) + return 0; + + bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE; + + if (dev->caps & CAP_BREAKINPUT_POLARITY) + bdtr |= TIM_BDTR_BKE; + + if (dev->polarity) + bdtr |= TIM_BDTR_BKP; + + regmap_update_bits(dev->regmap, TIM_BDTR, + TIM_BDTR_MOE | TIM_BDTR_AOE | + TIM_BDTR_BKP | TIM_BDTR_BKE, + bdtr); + + return 0; +} + +static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + u32 mask; + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip); + + mask = TIM_CCER_CC1P << (pwm->hwpwm * 4); + if (dev->caps & CAP_COMPLEMENTARY) + mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4); + + regmap_update_bits(dev->regmap, TIM_CCER, mask, + polarity == PWM_POLARITY_NORMAL ? 0 : mask); + + return 0; +} + +static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + u32 mask; + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip); + + clk_enable(dev->clk); + + /* Enable channel */ + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4); + if (dev->caps & CAP_COMPLEMENTARY) + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4); + + regmap_update_bits(dev->regmap, TIM_CCER, mask, mask); + + /* Make sure that registers are updated */ + regmap_update_bits(dev->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + + /* Enable controller */ + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); + + return 0; +} + +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + u32 mask; + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip); + + /* Disable channel */ + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4); + if (dev->caps & CAP_COMPLEMENTARY) + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4); + + regmap_update_bits(dev->regmap, TIM_CCER, mask, 0); + + /* When all channels are disabled, we can disable the controller */ + if (!__active_channels(dev)) + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0); + + clk_disable(dev->clk); +} + +static const struct pwm_ops stm32pwm_ops = { + .config = stm32_pwm_config, + .set_polarity = stm32_pwm_set_polarity, + .enable = stm32_pwm_enable, + .disable = stm32_pwm_disable, +}; + +static int stm32_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct stm32_gptimer_dev *mfd = dev_get_drvdata(pdev->dev.parent); + struct stm32_pwm_dev *pwm; + int ret; + + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->regmap = mfd->regmap; + pwm->clk = mfd->clk; + + if (!pwm->regmap || !pwm->clk) + return -EINVAL; + + if (of_property_read_bool(np, "st,complementary")) + pwm->caps |= CAP_COMPLEMENTARY; + + if (of_property_read_bool(np, "st,32bits-counter")) + pwm->caps |= CAP_32BITS_COUNTER; + + if (of_property_read_bool(np, "st,breakinput")) + pwm->caps |= CAP_BREAKINPUT; + + if (!of_property_read_u32(np, "st,breakinput-polarity", &pwm->polarity)) + pwm->caps |= CAP_BREAKINPUT_POLARITY; + + of_property_read_u32(np, "st,pwm-num-chan", &pwm->npwm); + + pwm->chip.base = -1; + pwm->chip.dev = dev; + pwm->chip.ops = &stm32pwm_ops; + pwm->chip.npwm = pwm->npwm; + + ret = pwmchip_add(&pwm->chip); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int stm32_pwm_remove(struct platform_device *pdev) +{ + struct stm32_pwm_dev *pwm = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < pwm->npwm; i++) + pwm_disable(&pwm->chip.pwms[i]); + + pwmchip_remove(&pwm->chip); + + return 0; +} + +static const struct of_device_id stm32_pwm_of_match[] = { + { + .compatible = "st,stm32-pwm", + }, +}; +MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); + +static struct platform_driver stm32_pwm_driver = { + .probe = stm32_pwm_probe, + .remove = stm32_pwm_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = stm32_pwm_of_match, + }, +}; +module_platform_driver(stm32_pwm_driver); + +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); +MODULE_LICENSE("GPL");