| Message ID | 20241108104958.2931943-4-claudiu.beznea.uj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,01/25] clk: renesas: r9a08g045-cpg: Add clocks, resets and power domains support for SSI | expand |
Hi Claudiu, Thanks for the patch. > -----Original Message----- > From: Claudiu <claudiu.beznea@tuxon.dev> > Sent: 08 November 2024 10:50 > Subject: [PATCH v2 03/25] dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator > > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > There are some differences b/w 5L35023 and 5P35023 Versa3 clock generator variants but the same driver > could be used with minimal adjustments. The identified differences are PLL2 Fvco, the clock sel bit > for SE2 clock and different default values for some registers. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Cheers, Biju > --- > > Changes in v2: > - collected tags > > Documentation/devicetree/bindings/clock/renesas,5p35023.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > index 42b6f80613f3..162d38035188 100644 > --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > @@ -31,6 +31,7 @@ description: | > properties: > compatible: > enum: > + - renesas,5l35023 > - renesas,5p35023 > > reg: > -- > 2.39.2
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml index 42b6f80613f3..162d38035188 100644 --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -31,6 +31,7 @@ description: | properties: compatible: enum: + - renesas,5l35023 - renesas,5p35023 reg: