Message ID | 20241113133540.2005850-4-claudiu.beznea.uj@bp.renesas.com |
---|---|
State | New |
Headers | show |
Series | [v3,01/25] clk: renesas: r9a08g045-cpg: Add clocks, resets and power domains support for SSI | expand |
On Wed, Nov 13, 2024 at 2:35 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > There are some differences b/w 5L35023 and 5P35023 Versa3 clock > generator variants but the same driver could be used with minimal > adjustments. The identified differences are PLL2 Fvco, the clock sel > bit for SE2 clock and different default values for some registers. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml index 42b6f80613f3..162d38035188 100644 --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -31,6 +31,7 @@ description: | properties: compatible: enum: + - renesas,5l35023 - renesas,5p35023 reg: