diff mbox series

[RISU] risugen/aarch64: FCMP*Z* require rm == 0

Message ID 20241117001125.497129-1-richard.henderson@linaro.org
State New
Headers show
Series [RISU] risugen/aarch64: FCMP*Z* require rm == 0 | expand

Commit Message

Richard Henderson Nov. 17, 2024, 12:11 a.m. UTC 
Do not generate rm other than 0, as it is UNPREDICTABLE
whether the instruction will trap as invalid.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 aarch64.risu | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Peter Maydell Nov. 18, 2024, 10:32 a.m. UTC | #1 
On Sun, 17 Nov 2024 at 00:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Do not generate rm other than 0, as it is UNPREDICTABLE
> whether the instruction will trap as invalid.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  aarch64.risu | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Applied to risu upstream, thanks.

-- PMM
diff mbox series

Patch

diff --git a/aarch64.risu b/aarch64.risu
index 87d9c72..bfea659 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2632,14 +2632,14 @@  SHA256SU0 A64_V 0101 1110 sz:2 10100 00010 10 rn:5 rd:5
 @DataProcessingScalarFP
 
 FCMPS A64_V 000 11110 00 1 rm:5 00 1000 rn:5 00 000
-FCMPZS A64_V 000 11110 00 1 rm:5 00 1000 rn:5 01 000
+FCMPZS A64_V 000 11110 00 1 00000 00 1000 rn:5 01 000
 FCMPES A64_V 000 11110 00 1 rm:5 00 1000 rn:5 10 000
-FCMPEZS A64_V 000 11110 00 1 rm:5 00 1000 rn:5 11 000
+FCMPEZS A64_V 000 11110 00 1 00000 00 1000 rn:5 11 000
 
 FCMPD A64_V 000 11110 01 1 rm:5 00 1000 rn:5 00 000
-FCMPZD A64_V 000 11110 01 1 rm:5 00 1000 rn:5 01 000
+FCMPZD A64_V 000 11110 01 1 00000 00 1000 rn:5 01 000
 FCMPED A64_V 000 11110 01 1 rm:5 00 1000 rn:5 10 000
-FCMPEZD A64_V 000 11110 01 1 rm:5 00 1000 rn:5 11 000
+FCMPEZD A64_V 000 11110 01 1 00000 00 1000 rn:5 11 000
 
 # Unallocated Encodings and ReservedValues
 FCMP_RES1 A64_V mos:3 11110 0 type:1 1 rm:5 00 1000 rn:5 opc:2 000 \