| Message ID | 20241115134401.3893008-9-claudiu.beznea.uj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for the rest of Renesas RZ/G3S serial interfaces | expand |
Hi Claudiu, On Fri, Nov 15, 2024 at 2:50 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the > PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod.dtso > @@ -0,0 +1,48 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts So you plan to describe all 3 PMOD interfaces in a single overlay? The board has: 1. PMOD0 - Type-2A, 2. PMOD1 - Tpye-3A, 3. PMOD1 - Type 6A. Wouldn't it be more convenient to have separate overlays for each port, so you can more easily use them as e.g. Type-1(A) (GPIO only)? BTW, naming both the second and third port "PMOD1" in the schematics, and differentiating them by their type, was definitely a bad idea. How can you distinguish between Type-1(A) on the second or third port? > + * > + * Copyright (C) 2024 Renesas Electronics Corp. > + * > + * > + * [Connection] > + * > + * SMARC Carrier II EVK > + * +--------------------------------------------+ > + * |PMOD1_3A (PMOD1 PIN HEADER) | > + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | > + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | > + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | > + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | > + * | GND (pin5) (pin11) GND | > + * | PWR_PMOD1 (pin6) (pin12) GND | > + * +--------------------------------------------+ This depends not only on CONFIG_SW3 (for RXD only), but also on SW_OPT_MUX4 (SW_SER0_PMOD=L gates all 4 SCIF1 signals). While including "rzg3s-smarc-switches.h" for (out-of-tree) overlay configfs is not really needed, please document the switches in the comments. As this is included in r9a08g045s33-smarc-pmod.dtb, you may still want to include "rzg3s-smarc-switches.h". > + * > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > + > +&{/} { > + aliases { > + serial0 = "/soc/serial@1004bc00"; Note that configuring aliases doesn't work in dynamic overlays (but we don't care in upstream). However, this is also wired on the Carrier board to the M2 slot when SW_SER0_PMOD is low. so I think it makes sense to have the alias unconditionally in rzg3s-smarc.dtsi instead. > + }; Gr{oetje,eeting}s, Geert
Hi, Geert, On 09.12.2024 12:44, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Fri, Nov 15, 2024 at 2:50 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Add DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the >> PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Thanks for your patch! > >> --- /dev/null >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod.dtso >> @@ -0,0 +1,48 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts > > So you plan to describe all 3 PMOD interfaces in a single overlay? > The board has: > 1. PMOD0 - Type-2A, > 2. PMOD1 - Tpye-3A, > 3. PMOD1 - Type 6A. > Wouldn't it be more convenient to have separate overlays for each port, > so you can more easily use them as e.g. Type-1(A) (GPIO only)? That would be better, indeed. > > BTW, naming both the second and third port "PMOD1" in the schematics, > and differentiating them by their type, was definitely a bad idea. > How can you distinguish between Type-1(A) on the second or third port? > >> + * >> + * Copyright (C) 2024 Renesas Electronics Corp. >> + * >> + * >> + * [Connection] >> + * >> + * SMARC Carrier II EVK >> + * +--------------------------------------------+ >> + * |PMOD1_3A (PMOD1 PIN HEADER) | >> + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | >> + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | >> + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | >> + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | >> + * | GND (pin5) (pin11) GND | >> + * | PWR_PMOD1 (pin6) (pin12) GND | >> + * +--------------------------------------------+ > > This depends not only on CONFIG_SW3 (for RXD only), but also on > SW_OPT_MUX4 (SW_SER0_PMOD=L gates all 4 SCIF1 signals). You're right! > While including "rzg3s-smarc-switches.h" for (out-of-tree) overlay > configfs is not really needed, please document the switches in the > comments. Sure! > As this is included in r9a08g045s33-smarc-pmod.dtb, you > may still want to include "rzg3s-smarc-switches.h". OK, I'll handle it in the next version. > >> + * >> + */ >> + >> +/dts-v1/; >> +/plugin/; >> + >> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> >> + >> +&{/} { >> + aliases { >> + serial0 = "/soc/serial@1004bc00"; > > Note that configuring aliases doesn't work in dynamic overlays > (but we don't care in upstream). > However, this is also wired on the Carrier board to the M2 slot when > SW_SER0_PMOD is low. so I think it makes sense to have the alias > unconditionally in rzg3s-smarc.dtsi instead. OK, I'll move it there. Thank you for your review, Claudiu > >> + }; > > Gr{oetje,eeting}s, > > Geert >
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 97228a3cb99c..7ad52630d350 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -137,6 +137,9 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a08g045s33-smarc-pmod.dtbo +r9a08g045s33-smarc-pmod-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod.dtbo +dtb-$(CONFIG_ARCH_R9A07G043) += r9a08g045s33-smarc-pmod.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod.dtso new file mode 100644 index 000000000000..7d637ab110e1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC Carrier II EVK + * +--------------------------------------------+ + * |PMOD1_3A (PMOD1 PIN HEADER) | + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | + * | GND (pin5) (pin11) GND | + * | PWR_PMOD1 (pin6) (pin12) GND | + * +--------------------------------------------+ + * + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +&{/} { + aliases { + serial0 = "/soc/serial@1004bc00"; + }; +}; + +&pinctrl { + scif1_pins: scif1-pins { + pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */ + <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */ + <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS */ + <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS */ + }; +}; + +&scif1 { + pinctrl-names = "default"; + pinctrl-0 = <&scif1_pins>; + uart-has-rtscts; + status = "okay"; +};