diff mbox series

[v3,6/8] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches

Message ID 20241115134401.3893008-7-claudiu.beznea.uj@bp.renesas.com
State New
Headers show
Series Add support for the rest of Renesas RZ/G3S serial interfaces | expand

Commit Message

Claudiu Beznea Nov. 15, 2024, 1:43 p.m. UTC 
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

There are different switches available on both the RZ/G3S SMARC Module and
RZ SMARC Carrier II boards. These switches are used to route different SoC
signals to different parts available on board.

These switches are described in device trees through macros. These macros
are set accordingly such that the resulted compiled dtb to describe the
on-board switches states.

Based on the SW_CONFIG3 switch state (populated on the module board), the
SCIF3 SoC interface is routed or not to an U(S)ART pin header available on
the carrier board. As the SCIF3 is accessible through the carrier board,
the device tree enables it in the carrier DTS. To be able to cope with
these type of configurations, add a header file where all the on-board
switches can be described and shared accordingly between module and carrier
board.

Commit prepares the code to enable SCIF3 on the RZ/G3S carrier device
tree.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v3:
- none

Changes in v2:
- none

 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     | 20 +-----------
 .../boot/dts/renesas/rzg3s-smarc-switches.h   | 32 +++++++++++++++++++
 2 files changed, 33 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h

Comments

Rob Herring Nov. 19, 2024, 4:23 p.m. UTC | #1 
On Fri, Nov 15, 2024 at 03:43:59PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> There are different switches available on both the RZ/G3S SMARC Module and
> RZ SMARC Carrier II boards. These switches are used to route different SoC
> signals to different parts available on board.
> 
> These switches are described in device trees through macros. These macros
> are set accordingly such that the resulted compiled dtb to describe the
> on-board switches states.
> 
> Based on the SW_CONFIG3 switch state (populated on the module board), the
> SCIF3 SoC interface is routed or not to an U(S)ART pin header available on
> the carrier board. As the SCIF3 is accessible through the carrier board,
> the device tree enables it in the carrier DTS. To be able to cope with
> these type of configurations, add a header file where all the on-board
> switches can be described and shared accordingly between module and carrier
> board.
> 
> Commit prepares the code to enable SCIF3 on the RZ/G3S carrier device
> tree.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> 
> Changes in v3:
> - none
> 
> Changes in v2:
> - none
> 
>  .../boot/dts/renesas/rzg3s-smarc-som.dtsi     | 20 +-----------
>  .../boot/dts/renesas/rzg3s-smarc-switches.h   | 32 +++++++++++++++++++
>  2 files changed, 33 insertions(+), 19 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
> 
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> index 55c72c8a0735..5c88e130c89e 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -9,25 +9,7 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>  
> -/*
> - * On-board switches' states:
> - * @SW_OFF: switch's state is OFF
> - * @SW_ON:  switch's state is ON
> - */
> -#define SW_OFF		0
> -#define SW_ON		1
> -
> -/*
> - * SW_CONFIG[x] switches' states:
> - * @SW_CONFIG2:
> - *	SW_OFF - SD0 is connected to eMMC
> - *	SW_ON  - SD0 is connected to uSD0 card
> - * @SW_CONFIG3:
> - *	SW_OFF - SD2 is connected to SoC
> - *	SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
> - */
> -#define SW_CONFIG2	SW_OFF
> -#define SW_CONFIG3	SW_ON
> +#include "rzg3s-smarc-switches.h"
>  
>  / {
>  	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
> new file mode 100644
> index 000000000000..e2d9b953f627
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Use the same license as the .dtsi file.

> +/*
> + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II
> + * boards.
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +
> +#ifndef __RZG3S_SMARC_SWITCHES__
> +#define __RZG3S_SMARC_SWITCHES__
> +
> +/*
> + * On-board switches' states:
> + * @SW_OFF: switch's state is OFF
> + * @SW_ON:  switch's state is ON
> + */
> +#define SW_OFF		0
> +#define SW_ON		1
> +
> +/*
> + * SW_CONFIG[x] switches' states:
> + * @SW_CONFIG2:
> + *	SW_OFF - SD0 is connected to eMMC
> + *	SW_ON  - SD0 is connected to uSD0 card
> + * @SW_CONFIG3:
> + *	SW_OFF - SD2 is connected to SoC
> + *	SW_ON  - SCIF3, SSI3, IRQ0, IRQ1 connected to SoC
> + */
> +#define SW_CONFIG2	SW_OFF
> +#define SW_CONFIG3	SW_ON
> +
> +#endif /* __RZG3S_SMARC_SWITCHES__ */
> -- 
> 2.39.2
>
Geert Uytterhoeven Dec. 9, 2024, 10:09 a.m. UTC | #2 
Hi Claudiu,

On Fri, Nov 15, 2024 at 2:50 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> There are different switches available on both the RZ/G3S SMARC Module and
> RZ SMARC Carrier II boards. These switches are used to route different SoC
> signals to different parts available on board.
>
> These switches are described in device trees through macros. These macros
> are set accordingly such that the resulted compiled dtb to describe the
> on-board switches states.
>
> Based on the SW_CONFIG3 switch state (populated on the module board), the
> SCIF3 SoC interface is routed or not to an U(S)ART pin header available on
> the carrier board. As the SCIF3 is accessible through the carrier board,
> the device tree enables it in the carrier DTS. To be able to cope with
> these type of configurations, add a header file where all the on-board
> switches can be described and shared accordingly between module and carrier
> board.
>
> Commit prepares the code to enable SCIF3 on the RZ/G3S carrier device
> tree.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -9,25 +9,7 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>
> -/*
> - * On-board switches' states:
> - * @SW_OFF: switch's state is OFF
> - * @SW_ON:  switch's state is ON
> - */
> -#define SW_OFF         0
> -#define SW_ON          1
> -
> -/*
> - * SW_CONFIG[x] switches' states:
> - * @SW_CONFIG2:
> - *     SW_OFF - SD0 is connected to eMMC
> - *     SW_ON  - SD0 is connected to uSD0 card
> - * @SW_CONFIG3:
> - *     SW_OFF - SD2 is connected to SoC
> - *     SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
> - */
> -#define SW_CONFIG2     SW_OFF
> -#define SW_CONFIG3     SW_ON
> +#include "rzg3s-smarc-switches.h"
>
>  / {
>         compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
> new file mode 100644
> index 000000000000..e2d9b953f627
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

I agree with Rob about the license.

> +/*
> + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II
> + * boards.
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +
> +#ifndef __RZG3S_SMARC_SWITCHES__
> +#define __RZG3S_SMARC_SWITCHES__
> +
> +/*
> + * On-board switches' states:
> + * @SW_OFF: switch's state is OFF
> + * @SW_ON:  switch's state is ON
> + */
> +#define SW_OFF         0
> +#define SW_ON          1
> +
> +/*
> + * SW_CONFIG[x] switches' states:
> + * @SW_CONFIG2:
> + *     SW_OFF - SD0 is connected to eMMC
> + *     SW_ON  - SD0 is connected to uSD0 card
> + * @SW_CONFIG3:
> + *     SW_OFF - SD2 is connected to SoC
> + *     SW_ON  - SCIF3, SSI3, IRQ0, IRQ1 connected to SoC

Note that the original comment above says "SCIF1, SSI0", and looking
at the schematics (IC7 and IC8 controlled by SW_SD2_EN#), that is
actually correct?

> + */
> +#define SW_CONFIG2     SW_OFF
> +#define SW_CONFIG3     SW_ON
> +
> +#endif /* __RZG3S_SMARC_SWITCHES__ */

Gr{oetje,eeting}s,

                        Geert
Claudiu Beznea Dec. 9, 2024, 12:10 p.m. UTC | #3 
Hi, Geert,

On 09.12.2024 12:09, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Fri, Nov 15, 2024 at 2:50 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> There are different switches available on both the RZ/G3S SMARC Module and
>> RZ SMARC Carrier II boards. These switches are used to route different SoC
>> signals to different parts available on board.
>>
>> These switches are described in device trees through macros. These macros
>> are set accordingly such that the resulted compiled dtb to describe the
>> on-board switches states.
>>
>> Based on the SW_CONFIG3 switch state (populated on the module board), the
>> SCIF3 SoC interface is routed or not to an U(S)ART pin header available on
>> the carrier board. As the SCIF3 is accessible through the carrier board,
>> the device tree enables it in the carrier DTS. To be able to cope with
>> these type of configurations, add a header file where all the on-board
>> switches can be described and shared accordingly between module and carrier
>> board.
>>
>> Commit prepares the code to enable SCIF3 on the RZ/G3S carrier device
>> tree.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
>> @@ -9,25 +9,7 @@
>>  #include <dt-bindings/gpio/gpio.h>
>>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>>
>> -/*
>> - * On-board switches' states:
>> - * @SW_OFF: switch's state is OFF
>> - * @SW_ON:  switch's state is ON
>> - */
>> -#define SW_OFF         0
>> -#define SW_ON          1
>> -
>> -/*
>> - * SW_CONFIG[x] switches' states:
>> - * @SW_CONFIG2:
>> - *     SW_OFF - SD0 is connected to eMMC
>> - *     SW_ON  - SD0 is connected to uSD0 card
>> - * @SW_CONFIG3:
>> - *     SW_OFF - SD2 is connected to SoC
>> - *     SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
>> - */
>> -#define SW_CONFIG2     SW_OFF
>> -#define SW_CONFIG3     SW_ON
>> +#include "rzg3s-smarc-switches.h"
>>
>>  / {
>>         compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
>> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
>> new file mode 100644
>> index 000000000000..e2d9b953f627
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
>> @@ -0,0 +1,32 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
> 
> I agree with Rob about the license.
> 
>> +/*
>> + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II
>> + * boards.
>> + *
>> + * Copyright (C) 2024 Renesas Electronics Corp.
>> + */
>> +
>> +#ifndef __RZG3S_SMARC_SWITCHES__
>> +#define __RZG3S_SMARC_SWITCHES__
>> +
>> +/*
>> + * On-board switches' states:
>> + * @SW_OFF: switch's state is OFF
>> + * @SW_ON:  switch's state is ON
>> + */
>> +#define SW_OFF         0
>> +#define SW_ON          1
>> +
>> +/*
>> + * SW_CONFIG[x] switches' states:
>> + * @SW_CONFIG2:
>> + *     SW_OFF - SD0 is connected to eMMC
>> + *     SW_ON  - SD0 is connected to uSD0 card
>> + * @SW_CONFIG3:
>> + *     SW_OFF - SD2 is connected to SoC
>> + *     SW_ON  - SCIF3, SSI3, IRQ0, IRQ1 connected to SoC
> 
> Note that the original comment above says "SCIF1, SSI0", and looking
> at the schematics (IC7 and IC8 controlled by SW_SD2_EN#), that is
> actually correct?

You're right, I'm not sure why I've changed it. I'll fix it in the next
version.

Thank  you for your review,
Claudiu

> 
>> + */
>> +#define SW_CONFIG2     SW_OFF
>> +#define SW_CONFIG3     SW_ON
>> +
>> +#endif /* __RZG3S_SMARC_SWITCHES__ */
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 55c72c8a0735..5c88e130c89e 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -9,25 +9,7 @@ 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
-/*
- * On-board switches' states:
- * @SW_OFF: switch's state is OFF
- * @SW_ON:  switch's state is ON
- */
-#define SW_OFF		0
-#define SW_ON		1
-
-/*
- * SW_CONFIG[x] switches' states:
- * @SW_CONFIG2:
- *	SW_OFF - SD0 is connected to eMMC
- *	SW_ON  - SD0 is connected to uSD0 card
- * @SW_CONFIG3:
- *	SW_OFF - SD2 is connected to SoC
- *	SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
- */
-#define SW_CONFIG2	SW_OFF
-#define SW_CONFIG3	SW_ON
+#include "rzg3s-smarc-switches.h"
 
 / {
 	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
new file mode 100644
index 000000000000..e2d9b953f627
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -0,0 +1,32 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II
+ * boards.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#ifndef __RZG3S_SMARC_SWITCHES__
+#define __RZG3S_SMARC_SWITCHES__
+
+/*
+ * On-board switches' states:
+ * @SW_OFF: switch's state is OFF
+ * @SW_ON:  switch's state is ON
+ */
+#define SW_OFF		0
+#define SW_ON		1
+
+/*
+ * SW_CONFIG[x] switches' states:
+ * @SW_CONFIG2:
+ *	SW_OFF - SD0 is connected to eMMC
+ *	SW_ON  - SD0 is connected to uSD0 card
+ * @SW_CONFIG3:
+ *	SW_OFF - SD2 is connected to SoC
+ *	SW_ON  - SCIF3, SSI3, IRQ0, IRQ1 connected to SoC
+ */
+#define SW_CONFIG2	SW_OFF
+#define SW_CONFIG3	SW_ON
+
+#endif /* __RZG3S_SMARC_SWITCHES__ */