@@ -40,7 +40,9 @@
#include "mgb4_trigger.h"
#include "mgb4_core.h"
-#define MGB4_USER_IRQS 16
+#define MGB4_USER_IRQS 16
+#define MGB4_MGB4_BAR_ID 0
+#define MGB4_XDMA_BAR_ID 1
#define DIGITEQ_VID 0x1ed8
#define T100_DID 0x0101
@@ -18,9 +18,6 @@
#define MGB4_VIN_DEVICES 2
#define MGB4_VOUT_DEVICES 2
-#define MGB4_MGB4_BAR_ID 0
-#define MGB4_XDMA_BAR_ID 1
-
#define MGB4_IS_GMSL(mgbdev) \
((mgbdev)->module_version >> 4 == 2)
#define MGB4_IS_FPDL3(mgbdev) \
@@ -24,10 +24,6 @@
#include "mgb4_cmt.h"
#include "mgb4_vout.h"
-#define DEFAULT_WIDTH 1280
-#define DEFAULT_HEIGHT 640
-#define DEFAULT_PERIOD (MGB4_HW_FREQ / 60)
-
ATTRIBUTE_GROUPS(mgb4_fpdl3_out);
ATTRIBUTE_GROUPS(mgb4_gmsl_out);
@@ -664,11 +660,10 @@ static void fpga_init(struct mgb4_vout_dev *voutdev)
const struct mgb4_vout_regs *regs = &voutdev->config->regs;
mgb4_write_reg(video, regs->config, 0x00000011);
- mgb4_write_reg(video, regs->resolution,
- (DEFAULT_WIDTH << 16) | DEFAULT_HEIGHT);
+ mgb4_write_reg(video, regs->resolution, (1280 << 16) | 640);
mgb4_write_reg(video, regs->hsync, 0x00283232);
mgb4_write_reg(video, regs->vsync, 0x40141F1E);
- mgb4_write_reg(video, regs->frame_limit, DEFAULT_PERIOD);
+ mgb4_write_reg(video, regs->frame_limit, MGB4_HW_FREQ / 60);
mgb4_write_reg(video, regs->padding, 0x00000000);
voutdev->freq = mgb4_cmt_set_vout_freq(voutdev, 61150 >> 1) << 1;