| Message ID | 20241122124505.1688436-5-quic_mmanikan@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add SPI0 support for IPQ5424 | expand |
On 22.11.2024 1:45 PM, Manikanta Mylavarapu wrote: > Enable the SPI0 node and configure the associated gpio pins. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 45 +++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > index d4d31026a026..6256216ca764 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > @@ -23,6 +23,36 @@ &sleep_clk { > }; > > &tlmm { > + spi0_default_state: spi0-default-state { > + clk-pins { > + pins = "gpio6"; > + function = "spi0_clk"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + > + cs-pins { > + pins = "gpio7"; > + function = "spi0_cs"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + miso-pins { > + pins = "gpio8"; > + function = "spi0_miso"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + > + mosi-pins { > + pins = "gpio9"; > + function = "spi0_mosi"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + }; > + > sdc_default_state: sdc-default-state { > clk-pins { > pins = "gpio5"; > @@ -57,3 +87,18 @@ &xo_board { > clock-frequency = <24000000>; > }; > > +&qupv3 { > + spi0: spi@1a90000 { &spi0 { pinctrl-0 = <.. ... }; KonraD
On 12/5/2024 11:00 PM, Konrad Dybcio wrote: > On 22.11.2024 1:45 PM, Manikanta Mylavarapu wrote: >> Enable the SPI0 node and configure the associated gpio pins. >> >> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 45 +++++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts >> index d4d31026a026..6256216ca764 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts >> @@ -23,6 +23,36 @@ &sleep_clk { >> }; >> >> &tlmm { >> + spi0_default_state: spi0-default-state { >> + clk-pins { >> + pins = "gpio6"; >> + function = "spi0_clk"; >> + drive-strength = <8>; >> + bias-pull-down; >> + }; >> + >> + cs-pins { >> + pins = "gpio7"; >> + function = "spi0_cs"; >> + drive-strength = <8>; >> + bias-pull-up; >> + }; >> + >> + miso-pins { >> + pins = "gpio8"; >> + function = "spi0_miso"; >> + drive-strength = <8>; >> + bias-pull-down; >> + }; >> + >> + mosi-pins { >> + pins = "gpio9"; >> + function = "spi0_mosi"; >> + drive-strength = <8>; >> + bias-pull-down; >> + }; >> + }; >> + >> sdc_default_state: sdc-default-state { >> clk-pins { >> pins = "gpio5"; >> @@ -57,3 +87,18 @@ &xo_board { >> clock-frequency = <24000000>; >> }; >> >> +&qupv3 { >> + spi0: spi@1a90000 { > > &spi0 { > pinctrl-0 = <.. > ... > }; > Thanks for reviewing the patch. I will update in the next version. Thanks & Regards, Manikanta.
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index d4d31026a026..6256216ca764 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -23,6 +23,36 @@ &sleep_clk { }; &tlmm { + spi0_default_state: spi0-default-state { + clk-pins { + pins = "gpio6"; + function = "spi0_clk"; + drive-strength = <8>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio7"; + function = "spi0_cs"; + drive-strength = <8>; + bias-pull-up; + }; + + miso-pins { + pins = "gpio8"; + function = "spi0_miso"; + drive-strength = <8>; + bias-pull-down; + }; + + mosi-pins { + pins = "gpio9"; + function = "spi0_mosi"; + drive-strength = <8>; + bias-pull-down; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio5"; @@ -57,3 +87,18 @@ &xo_board { clock-frequency = <24000000>; }; +&qupv3 { + spi0: spi@1a90000 { + pinctrl-0 = <&spi0_default_state>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; + }; +};
Enable the SPI0 node and configure the associated gpio pins. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 45 +++++++++++++++++++++ 1 file changed, 45 insertions(+)