diff mbox series

[1/4] clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock

Message ID 20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org
State New
Headers show
Series clk: qcom: add PCIe clocks | expand

Commit Message

Neil Armstrong Nov. 25, 2024, 8:34 a.m. UTC 
The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.

Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/clk/qcom/clock-qcom.c | 19 +++++++++++++++++++
 drivers/clk/qcom/clock-qcom.h |  2 ++
 2 files changed, 21 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 25ca67e537d112dda236837d3d3984f9b666365e..7687bbe6a23b436e4ddf3b29d1c910062961126d 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -166,6 +166,25 @@  void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
 	clk_bcr_update(base + cmd_rcgr);
 }
 
+#define PHY_MUX_MASK		GENMASK(1, 0)
+#define PHY_MUX_PHY_SRC		0
+#define PHY_MUX_REF_SRC		2
+
+void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled)
+{
+	u32 cfg;
+
+	/* setup src select and divider */
+	cfg  = readl(base + cmd_rcgr);
+	cfg &= ~(PHY_MUX_MASK);
+	if (enabled)
+		cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC);
+	else
+		cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC);
+
+	writel(cfg, base + cmd_rcgr);
+}
+
 const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
 {
 	if (!f)
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 78d9b1d81ece1b3dd96b7bd0ab1a69fa016523b6..ff336dea39cf5cbe35f37f93669285897ba185a4 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -6,6 +6,7 @@ 
 #define _CLOCK_QCOM_H
 
 #include <asm/io.h>
+#include <linux/bitfield.h>
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
@@ -102,6 +103,7 @@  void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
 			  int div, int m, int n, int source, u8 mnd_width);
 void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
 		      int source);
+void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
 static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
 {