diff mbox series

[V3,2/2] arm64: dts: qcom: qcs8300: enable the inline crypto engine

Message ID 20241125065801.1751256-3-quic_yrangana@quicinc.com
State Superseded
Headers show
Series Enable Inline crypto engine for QCS8300 | expand

Commit Message

Yuvaraj Ranganathan Nov. 25, 2024, 6:58 a.m. UTC 
Add an ICE node to qcs8300 SoC description and enable it by adding a
phandle to the UFS node.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..ab91c3b7bba6 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -685,6 +685,7 @@  &mc_virt SLAVE_EBI1 0>,
 					<0 0>,
 					<0 0>,
 					<0 0>;
+			qcom,ice = <&ice>;
 			status = "disabled";
 		};
 
@@ -710,6 +711,13 @@  ufs_mem_phy: phy@1d87000 {
 			status = "disabled";
 		};
 
+		ice: crypto@1d88000 {
+			compatible = "qcom,qcs8300-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x20000>;