[PULL,16/72] target/x86: Set FloatInfZeroNaNRule explicitly

Message ID	20241211162004.2795499-17-peter.maydell@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:08 +0000 Message-Id: <20241211162004.2795499-17-peter.maydell@linaro.org> In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/72] hw/net/lan9118: Extract lan9118_phy \| expand [PULL,01/72] hw/net/lan9118: Extract lan9118_phy [PULL,02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations [PULL,03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register [PULL,04/72] hw/net/lan9118_phy: Reuse MII constants [PULL,05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement [PULL,06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd [PULL,07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd [PULL,08/72] softfloat: Allow runtime choice of inf * 0 + NaN result [PULL,09/72] tests/fp: Explicitly set inf-zero-nan rule [PULL,10/72] target/arm: Set FloatInfZeroNaNRule explicitly [PULL,11/72] target/s390: Set FloatInfZeroNaNRule explicitly [PULL,12/72] target/ppc: Set FloatInfZeroNaNRule explicitly [PULL,13/72] target/mips: Set FloatInfZeroNaNRule explicitly [PULL,14/72] target/sparc: Set FloatInfZeroNaNRule explicitly [PULL,15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly [PULL,16/72] target/x86: Set FloatInfZeroNaNRule explicitly [PULL,17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly [PULL,18/72] target/hppa: Set FloatInfZeroNaNRule explicitly [PULL,19/72] softfloat: Pass have_snan to pickNaNMulAdd [PULL,20/72] softfloat: Allow runtime choice of NaN propagation for muladd [PULL,21/72] tests/fp: Explicitly set 3-NaN propagation rule [PULL,22/72] target/arm: Set Float3NaNPropRule explicitly [PULL,23/72] target/loongarch: Set Float3NaNPropRule explicitly [PULL,24/72] target/ppc: Set Float3NaNPropRule explicitly [PULL,25/72] target/s390x: Set Float3NaNPropRule explicitly [PULL,26/72] target/sparc: Set Float3NaNPropRule explicitly [PULL,27/72] target/mips: Set Float3NaNPropRule explicitly [PULL,28/72] target/xtensa: Set Float3NaNPropRule explicitly [PULL,29/72] target/i386: Set Float3NaNPropRule explicitly [PULL,30/72] target/hppa: Set Float3NaNPropRule explicitly [PULL,31/72] fpu: Remove use_first_nan field from float_status [PULL,32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan() [PULL,33/72] softfloat: Create floatx80 default NaN from parts64_default_nan [PULL,34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers [PULL,35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status [PULL,36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg [PULL,37/72] target/sparc: Initialize local scratch float_status from env->fp_status [PULL,38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions [PULL,39/72] target/arm: Copy entire float_status in is_ebf [PULL,40/72] fpu: Allow runtime choice of default NaN value [PULL,41/72] tests/fp: Set default NaN pattern explicitly [PULL,42/72] target/microblaze: Set default NaN pattern explicitly [PULL,43/72] target/i386: Set default NaN pattern explicitly [PULL,44/72] target/hppa: Set default NaN pattern explicitly [PULL,45/72] target/alpha: Set default NaN pattern explicitly [PULL,46/72] target/arm: Set default NaN pattern explicitly [PULL,47/72] target/loongarch: Set default NaN pattern explicitly [PULL,48/72] target/m68k: Set default NaN pattern explicitly [PULL,49/72] target/mips: Set default NaN pattern explicitly [PULL,50/72] target/openrisc: Set default NaN pattern explicitly [PULL,51/72] target/ppc: Set default NaN pattern explicitly [PULL,52/72] target/sh4: Set default NaN pattern explicitly [PULL,53/72] target/rx: Set default NaN pattern explicitly [PULL,54/72] target/s390x: Set default NaN pattern explicitly [PULL,55/72] target/sparc: Set default NaN pattern explicitly [PULL,56/72] target/xtensa: Set default NaN pattern explicitly [PULL,57/72] target/hexagon: Set default NaN pattern explicitly [PULL,58/72] target/riscv: Set default NaN pattern explicitly [PULL,59/72] target/tricore: Set default NaN pattern explicitly [PULL,60/72] fpu: Remove default handling for dnan_pattern [PULL,61/72] softfloat: Inline pickNaNMulAdd [PULL,62/72] softfloat: Use goto for default nan case in pick_nan_muladd [PULL,63/72] softfloat: Remove which from parts_pick_nan_muladd [PULL,64/72] softfloat: Pad array size in pick_nan_muladd [PULL,65/72] softfloat: Move propagateFloatx80NaN to softfloat.c [PULL,66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN [PULL,67/72] softfloat: Inline pickNaN [PULL,68/72] softfloat: Share code between parts_pick_nan cases [PULL,69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed [PULL,70/72] softfloat: Replace WHICH with RET in parts_pick_nan [PULL,71/72] MAINTAINERS: update email address for Leif Lindholm [PULL,72/72] MAINTAINERS: Add correct email address for Vikram Garhwal

Message ID

20241211162004.2795499-17-peter.maydell@linaro.org

State

New

Headers

Received-SPF: pass (google.com: domain of
 qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as
 permitted sender) client-ip=209.51.188.17;
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
Date: Wed, 11 Dec 2024 16:19:08 +0000
Message-Id: <20241211162004.2795499-17-peter.maydell@linaro.org>
In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org>
References: <20241211162004.2795499-1-peter.maydell@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Received-SPF: pass client-ip=2a00:1450:4864:20::32b;
 envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
 DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
 RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,
 SPF_PASS=-0.001 autolearn=ham autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org

Series

[PULL,01/72] hw/net/lan9118: Extract lan9118_phy | expand

Commit Message

Peter Maydell Dec. 11, 2024, 4:19 p.m. UTC

Set the FloatInfZeroNaNRule explicitly for the x86 target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
---
 target/i386/tcg/fpu_helper.c   | 7 +++++++
 fpu/softfloat-specialize.c.inc | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 53b49bb2977..3295753e075 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -173,6 +173,13 @@  void cpu_init_fp_statuses(CPUX86State *env)
      */
     set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
     set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
+    /*
+     * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
+     * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
+     * specified -- for 0 * inf + NaN the input NaN is selected, and if
+     * there are multiple input NaNs they are selected in the order a, b, c.
+     */
+    set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
 }
 
 static inline uint8_t save_exception_flags(CPUX86State *env)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index 3062d19402d..ad4f7096d09 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -490,7 +490,7 @@  static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
          * Temporarily fall back to ifdef ladder
          */
 #if defined(TARGET_HPPA) || \
-    defined(TARGET_I386) || defined(TARGET_LOONGARCH)
+    defined(TARGET_LOONGARCH)
         /*
          * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
          * case sets InvalidOp and returns the input value 'c'

[PULL,16/72] target/x86: Set FloatInfZeroNaNRule explicitly

Commit Message

Patch