@@ -7955,98 +7955,68 @@ TRANS(SUB_r, do_addsub_reg, a, true, false)
TRANS(ADDS_r, do_addsub_reg, a, false, true)
TRANS(SUBS_r, do_addsub_reg, a, true, true)
-/* Data-processing (3 source)
- *
- * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
- * +--+------+-----------+------+------+----+------+------+------+
- * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
- * +--+------+-----------+------+------+----+------+------+------+
- */
-static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
+static bool do_mulh(DisasContext *s, arg_rrr *a,
+ void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int ra = extract32(insn, 10, 5);
- int rm = extract32(insn, 16, 5);
- int op_id = (extract32(insn, 29, 3) << 4) |
- (extract32(insn, 21, 3) << 1) |
- extract32(insn, 15, 1);
- bool sf = extract32(insn, 31, 1);
- bool is_sub = extract32(op_id, 0, 1);
- bool is_high = extract32(op_id, 2, 1);
- bool is_signed = false;
- TCGv_i64 tcg_op1;
- TCGv_i64 tcg_op2;
- TCGv_i64 tcg_tmp;
+ TCGv_i64 discard = tcg_temp_new_i64();
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ TCGv_i64 tcg_rm = cpu_reg(s, a->rm);
- /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
- switch (op_id) {
- case 0x42: /* SMADDL */
- case 0x43: /* SMSUBL */
- case 0x44: /* SMULH */
- is_signed = true;
- break;
- case 0x0: /* MADD (32bit) */
- case 0x1: /* MSUB (32bit) */
- case 0x40: /* MADD (64bit) */
- case 0x41: /* MSUB (64bit) */
- case 0x4a: /* UMADDL */
- case 0x4b: /* UMSUBL */
- case 0x4c: /* UMULH */
- break;
- default:
- unallocated_encoding(s);
- return;
- }
+ fn(discard, tcg_rd, tcg_rn, tcg_rm);
+ return true;
+}
- if (is_high) {
- TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_rn = cpu_reg(s, rn);
- TCGv_i64 tcg_rm = cpu_reg(s, rm);
+TRANS(SMULH, do_mulh, a, tcg_gen_muls2_i64)
+TRANS(UMULH, do_mulh, a, tcg_gen_mulu2_i64)
- if (is_signed) {
- tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
- } else {
- tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
- }
- return;
- }
+static bool do_muladd(DisasContext *s, arg_rrrr *a,
+ bool sf, bool is_sub, MemOp mop)
+{
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_op1, tcg_op2;
- tcg_op1 = tcg_temp_new_i64();
- tcg_op2 = tcg_temp_new_i64();
- tcg_tmp = tcg_temp_new_i64();
-
- if (op_id < 0x42) {
- tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
- tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
+ if (mop == MO_64) {
+ tcg_op1 = cpu_reg(s, a->rn);
+ tcg_op2 = cpu_reg(s, a->rm);
} else {
- if (is_signed) {
- tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
- tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
- } else {
- tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
- tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
- }
+ tcg_op1 = tcg_temp_new_i64();
+ tcg_op2 = tcg_temp_new_i64();
+ tcg_gen_ext_i64(tcg_op1, cpu_reg(s, a->rn), mop);
+ tcg_gen_ext_i64(tcg_op2, cpu_reg(s, a->rm), mop);
}
- if (ra == 31 && !is_sub) {
+ if (a->ra == 31 && !is_sub) {
/* Special-case MADD with rA == XZR; it is the standard MUL alias */
- tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
+ tcg_gen_mul_i64(tcg_rd, tcg_op1, tcg_op2);
} else {
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i64 tcg_ra = cpu_reg(s, a->ra);
+
tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
if (is_sub) {
- tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
+ tcg_gen_sub_i64(tcg_rd, tcg_ra, tcg_tmp);
} else {
- tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
+ tcg_gen_add_i64(tcg_rd, tcg_ra, tcg_tmp);
}
}
if (!sf) {
- tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
+ return true;
}
+TRANS(MADD_w, do_muladd, a, false, false, MO_64)
+TRANS(MSUB_w, do_muladd, a, false, true, MO_64)
+TRANS(MADD_x, do_muladd, a, true, false, MO_64)
+TRANS(MSUB_x, do_muladd, a, true, true, MO_64)
+
+TRANS(SMADDL, do_muladd, a, true, false, MO_SL)
+TRANS(SMSUBL, do_muladd, a, true, true, MO_SL)
+TRANS(UMADDL, do_muladd, a, true, false, MO_UL)
+TRANS(UMSUBL, do_muladd, a, true, true, MO_UL)
+
/* Add/subtract (with carry)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
* +--+--+--+------------------------+------+-------------+------+-----+
@@ -8364,13 +8334,10 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
disas_cond_select(s, insn);
break;
- case 0x8 ... 0xf: /* (3 source) */
- disas_data_proc_3src(s, insn);
- break;
-
default:
do_unallocated:
case 0x6: /* Data-processing */
+ case 0x8 ... 0xf: /* (3 source) */
unallocated_encoding(s);
break;
}
@@ -753,6 +753,22 @@ SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext
# Conditional select
# Data Processing (3-source)
+&rrrr rd rn rm ra
+@rrrr . .. ........ rm:5 . ra:5 rn:5 rd:5 &rrrr
+
+MADD_w 0 00 11011000 ..... 0 ..... ..... ..... @rrrr
+MSUB_w 0 00 11011000 ..... 1 ..... ..... ..... @rrrr
+MADD_x 1 00 11011000 ..... 0 ..... ..... ..... @rrrr
+MSUB_x 1 00 11011000 ..... 1 ..... ..... ..... @rrrr
+
+SMADDL 1 00 11011001 ..... 0 ..... ..... ..... @rrrr
+SMSUBL 1 00 11011001 ..... 1 ..... ..... ..... @rrrr
+UMADDL 1 00 11011101 ..... 0 ..... ..... ..... @rrrr
+UMSUBL 1 00 11011101 ..... 1 ..... ..... ..... @rrrr
+
+SMULH 1 00 11011010 ..... 0 11111 ..... ..... @rrr
+UMULH 1 00 11011110 ..... 0 11111 ..... ..... @rrr
+
### Cryptographic AES
AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0