| Message ID | 20241211-topic-sm8x50-gpu-bw-vote-v5-5-6112f9f785ec@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm: adreno: add support for DDR bandwidth scaling via GMU | expand |
On 12.12.2024 10:36 PM, Neil Armstrong wrote: > On 12/12/2024 21:32, Konrad Dybcio wrote: >> On 11.12.2024 9:29 AM, Neil Armstrong wrote: >>> Now all the DDR bandwidth voting via the GPU Management Unit (GMU) >>> is in place, declare the Bus Control Modules (BCMs) and the >>> corresponding parameters in the GPU info struct. >>> >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++++++++++++++++++++++ >>> 1 file changed, 22 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..edffb7737a97b268bb2986d557969e651988a344 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1388,6 +1388,17 @@ static const struct adreno_info a7xx_gpus[] = { >>> .pwrup_reglist = &a7xx_pwrup_reglist, >>> .gmu_chipid = 0x7020100, >>> .gmu_cgc_mode = 0x00020202, >>> + .bcms = (const struct a6xx_bcm[]) { >>> + { .name = "SH0", .buswidth = 16 }, >> >> All a7xx targets use the same BCMs with the only difference being >> the ACV voting mask. You may want to make these non-anonymous structs. > > it can be done in a second step > >> >>> + { .name = "MC0", .buswidth = 4 }, >>> + { >>> + .name = "ACV", >>> + .fixed = true, >>> + .perfmode = BIT(3), >>> + .perfmode_bw = 16500000, >> >> I think perfmode is simply supposed to be set when bw == max_bw > > Not for a750 Akhil, is there any way to determine a suitable OPP for this dynamically? Konrad
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..edffb7737a97b268bb2986d557969e651988a344 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1388,6 +1388,17 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 4192 * SZ_1K, @@ -1432,6 +1443,17 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + { /* sentinel */ }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 3572 * SZ_1K,