| Message ID | 20241212-correct_gpio_ranges-v1-1-c5f20d61882f@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 | expand |
On Thu, 12 Dec 2024 17:24:00 +0800, Lijuan Gao wrote: > The QCS615 TLMM pin controller have the UFS_RESET pin, which is expected > to be wired to the reset pin of the primary UFS memory. Include it in > gpio-ranges so that the UFS driver can toggle it. > > Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer") > Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> > --- > Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml index 1ce4b5df584a..2791e578c1de 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -110,7 +110,7 @@ examples: <0x03c00000 0x300000>; reg-names = "east", "west", "south"; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&tlmm 0 0 123>; + gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; interrupt-controller;
The QCS615 TLMM pin controller have the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. Include it in gpio-ranges so that the UFS driver can toggle it. Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> --- Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)