Message ID | 20241219-topic-llcc_x1e_wrcache-v3-1-b9848d9c3d63@oss.qualcomm.com |
---|---|
State | New |
Headers | show |
Series | [v3] soc: qcom: llcc: Enable LLCC_WRCACHE at boot on X1 | expand |
On Thu, 19 Dec 2024 19:53:29 +0100, Konrad Dybcio wrote: > The Last Level Cache is split into many slices, each one of which can > be toggled on or off. > > Only certain slices are recommended to be turned on unconditionally, > in order to reach optimal performance/latency/power levels. > > Enable WRCACHE on X1 at boot, in accordance with internal > recommendations. > > [...] Applied, thanks! [1/1] soc: qcom: llcc: Enable LLCC_WRCACHE at boot on X1 commit: 35d8bc131de0f0f280f0db42499512d79f05f456 Best regards,
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 32c3bc887cefb87c296e3ba67a730c87fa2fa346..1560db00a01248197e5c2936e785a5ea77f74ad8 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -2997,20 +2997,21 @@ static const struct llcc_slice_config x1e80100_data[] = { .bonus_ways = 0xfff, .cache_mode = 0, }, { .usecase_id = LLCC_WRCACHE, .slice_id = 31, .max_cap = 1024, .priority = 1, .fixed_size = true, .bonus_ways = 0xfff, .cache_mode = 0, + .activate_on_init = true, }, { .usecase_id = LLCC_CAMEXP0, .slice_id = 4, .max_cap = 256, .priority = 4, .fixed_size = true, .bonus_ways = 0x3, .cache_mode = 0, }, { .usecase_id = LLCC_CAMEXP1,