diff mbox series

mailbox: qcom-ipcc: Reset CLEAR_ON_RECV_RD if set from boot firmware

Message ID 20241230070644.2512780-1-mojha@qti.qualcomm.com
State New
Headers show
Series mailbox: qcom-ipcc: Reset CLEAR_ON_RECV_RD if set from boot firmware | expand

Commit Message

Mukesh Ojha Dec. 30, 2024, 7:06 a.m. UTC 
From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>

For some SoCs, boot firmware is using the same IPCC instance used
by Linux and it has kept CLEAR_ON_RECV_RD set which basically means
interrupt pending registers are cleared when RECV_ID is read and the
register automatically updates to the next pending interrupt/client
status based on priority.

Clear the CLEAR_ON_RECV_RD if it is set from the boot firmware.

Signed-off-by: Mukesh Ojha <mojha@qti.qualcomm.com>
---
 drivers/mailbox/qcom-ipcc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Mukesh Ojha Dec. 30, 2024, 7:50 a.m. UTC | #1 
On Mon, Dec 30, 2024 at 12:36:44PM +0530, Mukesh Ojha wrote:
> From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> 
> For some SoCs, boot firmware is using the same IPCC instance used
> by Linux and it has kept CLEAR_ON_RECV_RD set which basically means
> interrupt pending registers are cleared when RECV_ID is read and the
> register automatically updates to the next pending interrupt/client
> status based on priority.
> 
> Clear the CLEAR_ON_RECV_RD if it is set from the boot firmware.
> 
> Signed-off-by: Mukesh Ojha <mojha@qti.qualcomm.com>

Very sorry for the spam, please ignore this patch, will send another one
with corrected email Id.

-Mukesh
>
diff mbox series

Patch

diff --git a/drivers/mailbox/qcom-ipcc.c b/drivers/mailbox/qcom-ipcc.c
index 14c7907c6632..0b17a38ea6bf 100644
--- a/drivers/mailbox/qcom-ipcc.c
+++ b/drivers/mailbox/qcom-ipcc.c
@@ -14,6 +14,7 @@ 
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 
 /* IPCC Register offsets */
+#define IPCC_REG_CONFIG			0x08
 #define IPCC_REG_SEND_ID		0x0c
 #define IPCC_REG_RECV_ID		0x10
 #define IPCC_REG_RECV_SIGNAL_ENABLE	0x14
@@ -21,6 +22,7 @@ 
 #define IPCC_REG_RECV_SIGNAL_CLEAR	0x1c
 #define IPCC_REG_CLIENT_CLEAR		0x38
 
+#define IPCC_CLEAR_ON_RECV_RD		BIT(0)
 #define IPCC_SIGNAL_ID_MASK		GENMASK(15, 0)
 #define IPCC_CLIENT_ID_MASK		GENMASK(31, 16)
 
@@ -274,6 +276,7 @@  static int qcom_ipcc_pm_resume(struct device *dev)
 static int qcom_ipcc_probe(struct platform_device *pdev)
 {
 	struct qcom_ipcc *ipcc;
+	u32 config_value;
 	static int id;
 	char *name;
 	int ret;
@@ -288,6 +291,19 @@  static int qcom_ipcc_probe(struct platform_device *pdev)
 	if (IS_ERR(ipcc->base))
 		return PTR_ERR(ipcc->base);
 
+	/*
+	 * It is possible that boot firmware is using the same IPCC instance
+	 * as of the HLOS and it has kept CLEAR_ON_RECV_RD set which basically
+	 * means Interrupt pending registers are cleared when RECV_ID is read.
+	 * The register automatically updates to the next pending interrupt/client
+	 * status based on priority.
+	 */
+	config_value = readl(ipcc->base + IPCC_REG_CONFIG);
+	if (config_value & IPCC_CLEAR_ON_RECV_RD) {
+		config_value &= ~(IPCC_CLEAR_ON_RECV_RD);
+		writel(config_value, ipcc->base + IPCC_REG_CONFIG);
+	}
+
 	ipcc->irq = platform_get_irq(pdev, 0);
 	if (ipcc->irq < 0)
 		return ipcc->irq;