| Message ID | 20250102190155.2593453-1-quic_nkumarsi@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add industrial mezzanine | expand |
On Fri, Jan 03, 2025 at 12:31:55AM +0530, Nirmesh Kumar Singh wrote: > From: Sahil Chandna <quic_chandna@quicinc.com> > > Add DTS support for Qualcomm qcs6490-rb3gen2 industrial mezzanine > board which uses QCS6490 SoC. This board enhances the capabilities of > QCS6490 rb3gen2 core kit. > > Signed-off-by: Sahil Chandna <quic_chandna@quicinc.com> > Signed-off-by: Nirmesh Kumar Singh <quic_nkumarsi@quicinc.com> > > --- > Changes in V2: > - Addressed comment by Konrad. > - Validated dts bindings with dtb_checks suggested by Krzysztof. > - Improved indentation/formatting. > - Fixed bug encountered during testing. > - Added dtb entry in makefile. > - Link to V1: https://lore.kernel.org/all/20241206065156.2573-1-quic_chandna@quicinc.com/ > > --- > --- > arch/arm64/boot/dts/qcom/Makefile | 5 +++ > .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 34 +++++++++++++++++++ > 2 files changed, 39 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 6ca8db4b8afe..7c61e9e330d7 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -111,6 +111,11 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb > + > +qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo > + > +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb > + > dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > new file mode 100644 > index 000000000000..7a067e8dc622 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > @@ -0,0 +1,34 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > +*/ > + > +/dts-v1/; > +/plugin/; > +#include <dt-bindings/clock/qcom,gcc-sc7280.h> > +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> > + > +/ { > +pm7250b-gpios { Something is very wrong here. This line has wrong indentation, this is a pinctrl node under the root node (instead of the corresponding pinctrl device), there seem to be no references to it, etc. > + pins = "gpio5"; Please use tabs instead of spaces for identation. > + function = "normal"; > + power-source = <1>; > + output-high; > + input-disable; > + bias-pull-up; > + qcom,drive-strength = <3>; > + }; > +}; > + > +&spi11 { > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + st33htpm0: tpm@0 { > + compatible = "st,st33htpm-spi","tcg,tpm_tis-spi"; Missing space > + reg = <0>; > + spi-max-frequency = <20000000>; > + Drop extra empty line. > + }; > +}; > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6ca8db4b8afe..7c61e9e330d7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -111,6 +111,11 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb + +qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso new file mode 100644 index 000000000000..7a067e8dc622 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +/dts-v1/; +/plugin/; +#include <dt-bindings/clock/qcom,gcc-sc7280.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { +pm7250b-gpios { + pins = "gpio5"; + function = "normal"; + power-source = <1>; + output-high; + input-disable; + bias-pull-up; + qcom,drive-strength = <3>; + }; +}; + +&spi11 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + st33htpm0: tpm@0 { + compatible = "st,st33htpm-spi","tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + + }; +};