Message ID | 20250104-sar2130p-nvmem-v3-3-a94e0b7de2fa@linaro.org |
---|---|
State | New |
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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223832c1bsm4261655e87.280.2025.01.03.22.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 22:19:23 -0800 (PST) From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Date: Sat, 04 Jan 2025 08:19:14 +0200 Subject: [PATCH v3 3/5] nvmem: core: update raw_len if the bit reading is required Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250104-sar2130p-nvmem-v3-3-a94e0b7de2fa@linaro.org> References: <20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org> In-Reply-To: <20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org> To: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org> Cc: Akhil P Oommen <quic_akhilpo@quicinc.com>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=988; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=sGP/szOES38d6mStd7Xz/BDPgQX6Jo4hmwT1BUTmpOs=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBneNLhnI1BmYlLUpy4fF+XLb8R2QFmSkEfV5UmG /LjBx6bNX2JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ3jS4QAKCRAU23LtvoBl uGRmD/9bD0kbhu5WeN4Ztgm4a92xL0AeFcVDBzoOR6adZJs7p9cQhPJUPOgjs8G+REiMml0HYdk 04+xsExMBEtQgSHm/hTMpJhkDg3jI5D90ytAVW1MPRfx8AMnwABLVtsZxl6APE4AwT16VNMOE28 T4UKxIfkdjS+wkxKUDT8FkvQ06h9E7d+1biBPSJhPinRcPmDv6asN81gR01/ulXKOJlOivRms+B khi6g/xLcF82i16A+EVfOCEemf5jqYKj5tv5G1tM4OsCKPH9ptS33l9FRJTtoVmfWw+iQVnVyFj ZXVQJlrYtenhJiV1nHZ60iK6FlpfGmMJAjQuXI9c8tLfqbXMCYwiGpqDc0HLhWGv7qHnDDnUh/l z4FQgMjhVHOyQaAfJ74NNyyLccBJZ6YQPilIpy0qN5yxHDaoa6fKUeObYqfSxQqEEahb31Icjnt F602eTkkoxGQCy6nyqoDDq3hSrKu00M3fYrE4Z8APsTvOqq9b690QAVBlGVfP3MlZ2EBYs/ybGO x4RlurwWAw0xmjFnaVZ7RTdCoJL3Wpc+egBXhO9/kXfNC+qlETJ56Ek3OMHbcO8NAVWt2qj9Q+n aUiUreS9bjgfmLrtmoQLkOg92ZsD2KUVBOuLmZhltbKnlT6DavoQQhEm3HdEHTI5s0NwzBgBaxK jh6suB/pYTS3AAw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A |
Series |
nvmem: qfprom: add Qualcomm SAR2130P support
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expand
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diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index a03a3006bd611ea6e91703cd19c2842bd4f56659..17b320bcbe207aed8a32aa2cc7d8dab9b58c13cf 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -591,9 +591,11 @@ static int nvmem_cell_info_to_nvmem_cell_entry_nodup(struct nvmem_device *nvmem, cell->nbits = info->nbits; cell->np = info->np; - if (cell->nbits) + if (cell->nbits) { cell->bytes = DIV_ROUND_UP(cell->nbits + cell->bit_offset, BITS_PER_BYTE); + cell->raw_len = ALIGN(cell->bytes, nvmem->word_size); + } if (!IS_ALIGNED(cell->offset, nvmem->stride)) { dev_err(&nvmem->dev,
If NVMEM cell uses bit offset or specifies bit truncation, update raw_len manually (following the cell->bytes update), ensuring that the NVMEM access is still word-aligned. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/nvmem/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)