diff mbox

fix for aarch64 sim FP stur bug

Message ID CABXYE2XMYdgCgjdQqaRb0LJi_otd55Bk7wgWQSyTCKZgu5Z3mA@mail.gmail.com
State New
Headers show

Commit Message

Jim Wilson Dec. 1, 2016, 7:36 a.m. UTC 
While debugging a gcc C testsuite failure on the aarch64 simulator, I
noticed that the support for FP stur instructions is broken.  They
accidentally have the two register operands swapped.  The problem can
be seen by comparing them with the equivalent FP str instructions.

I tested the fix by running the gcc C testsuite.  I get 3122
unexpected failures without the patch and 2856 unexpected failures
with the patch.

Jim

Comments

Nick Clifton Dec. 1, 2016, 9:13 a.m. UTC | #1 
Hi Jim,

> While debugging a gcc C testsuite failure on the aarch64 simulator, I

> noticed that the support for FP stur instructions is broken.  They

> accidentally have the two register operands swapped.  The problem can

> be seen by comparing them with the equivalent FP str instructions.

> 

> I tested the fix by running the gcc C testsuite.  I get 3122

> unexpected failures without the patch and 2856 unexpected failures

> with the patch.


Thanks for reporting and fixing this bug.

The patch is approved - please apply.

Cheers
  Nick
diff mbox

Patch

2016-11-30  Jim Wilson  <jim.wilson@linaro.org>

	* sim/aarch64/simulator.c (fsturs): Switch use of rn and st variables.
	(fsturd, fsturq): Likewise

diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index e5ada18..4fa5dc1 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -7497,8 +7497,8 @@  fsturs (sim_cpu *cpu, int32_t offset)
   unsigned int st = INSTR (4, 0);
 
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
-  aarch64_set_mem_u32 (cpu, aarch64_get_reg_u64 (cpu, st, 1) + offset,
-		       aarch64_get_vec_u32 (cpu, rn, 0));
+  aarch64_set_mem_u32 (cpu, aarch64_get_reg_u64 (cpu, rn, 1) + offset,
+		       aarch64_get_vec_u32 (cpu, st, 0));
 }
 
 /* Store 64 bit unscaled signed 9 bit.  */
@@ -7509,8 +7509,8 @@  fsturd (sim_cpu *cpu, int32_t offset)
   unsigned int st = INSTR (4, 0);
 
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
-  aarch64_set_mem_u64 (cpu, aarch64_get_reg_u64 (cpu, st, 1) + offset,
-		       aarch64_get_vec_u64 (cpu, rn, 0));
+  aarch64_set_mem_u64 (cpu, aarch64_get_reg_u64 (cpu, rn, 1) + offset,
+		       aarch64_get_vec_u64 (cpu, st, 0));
 }
 
 /* Store 128 bit unscaled signed 9 bit.  */
@@ -7522,9 +7522,9 @@  fsturq (sim_cpu *cpu, int32_t offset)
   FRegister a;
 
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
-  aarch64_get_FP_long_double (cpu, rn, & a);
+  aarch64_get_FP_long_double (cpu, st, & a);
   aarch64_set_mem_long_double (cpu,
-			       aarch64_get_reg_u64 (cpu, st, 1)
+			       aarch64_get_reg_u64 (cpu, rn, 1)
 			       + offset, a);
 }