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From: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
To: Georgi Djakov <djakov@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
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Subject: [PATCH V8 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for
SA8775P
Date: Wed, 5 Feb 2025 18:27:37 +0000
Message-ID: <20250205182743.915-2-quic_rlaggysh@quicinc.com>
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| Series |
Add EPSS L3 provider support on SA8775P SoC
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expand
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diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 4ac0863205b3..cd4bb912e0dc 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -28,6 +28,7 @@ properties: - const: qcom,osm-l3 - items: - enum: + - qcom,sa8775p-epss-l3 - qcom,sc7280-epss-l3 - qcom,sc8280xp-epss-l3 - qcom,sm6375-cpucp-l3
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SA8775P SoCs. The L3 instance on the SA8775P SoC is similar to those on SoCs like SM8250 and SC7280. These SoCs use the PERF register instead of L3_REG for programming the performance level, which is managed in the data associated with the target-specific compatibles. Since the hardware remains the same across all EPSS-supporting SoCs, the generic compatible is retained for all SoCs. Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+)