[48/61] target/arm: Implement SME2 FCVTZS, FCVTZU

Message ID	20250206195715.2150758-49-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 48/61] target/arm: Implement SME2 FCVTZS, FCVTZU Date: Thu, 6 Feb 2025 11:57:02 -0800 Message-ID: <20250206195715.2150758-49-richard.henderson@linaro.org> In-Reply-To: <20250206195715.2150758-1-richard.henderson@linaro.org> References: <20250206195715.2150758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/arm: Implement FEAT_SME2 \| expand [00/61] target/arm: Implement FEAT_SME2 [01/61] tcg: Add dbase argument to do_dup_store [02/61] tcg: Add dbase argument to do_dup [03/61] tcg: Add dbase argument to expand_clr [04/61] tcg: Add base arguments to check_overlap_[234] [05/61] tcg: Split out tcg_gen_gvec_2_var [06/61] tcg: Split out tcg_gen_gvec_3_var [07/61] tcg: Split out tcg_gen_gvec_mov_var [08/61] tcg: Split out tcg_gen_gvec_{add,sub}_var [09/61] target/arm: Introduce FPST_ZA, FPST_ZA_F16 [10/61] target/arm: Use FPST_ZA for sme_fmopa_[hsd] [11/61] target/arm: Rename zarray to za_state.za [12/61] target/arm: Add isar_feature_aa64_sme2* [13/61] target/arm: Add ZT0 [14/61] target/arm: Add zt0_excp_el to DisasContext [15/61] target/arm: Implement SME2 ZERO ZT0 [16/61] target/arm: Implement SME2 LDR/STR ZT0 [17/61] target/arm: Implement SME2 MOVT [18/61] target/arm: Split get_tile_rowcol argument tile_index [19/61] target/arm: Rename MOVA for translate [20/61] target/arm: Implement SME2 MOVA to/from tile, multiple registers [21/61] target/arm: Split out get_zarray [22/61] target/arm: Implement SME2 MOVA to/from array, multiple registers [23/61] target/arm: Implement SME2 BMOPA [24/61] target/arm: Implement SME2 SMOPS, UMOPS (2-way) [25/61] target/arm: Introduce gen_gvec_sve2_sqdmulh [26/61] target/arm: Implement SME2 Multiple and Single SVE Destructive [27/61] target/arm: Implement SME2 Multiple Vectors SVE Destructive [28/61] target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector) [29/61] target/arm: Implement SME2 ADD/SUB (array results, multiple vectors) [30/61] target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s [31/61] target/arm: Implement SME2 FMLAL, BFMLAL [32/61] target/arm: Implement SME2 FDOT [33/61] target/arm: Implement SME2 BFDOT [34/61] target/arm: Implement SME2 FVDOT, BFVDOT [35/61] target/arm: Rename helper_gvec_dot_[bh] to _4[bh] [36/61] target/arm: Remove helper_gvec_sudot_idx_4b [37/61] target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT [38/61] target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT [39/61] target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL [40/61] target/arm: Implement SME2 SMLALL, SMLSLL, UMLALL, UMLSLL [41/61] target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix [42/61] target/arm: Implement SME2 FMLA, FMLS [43/61] target/arm: Implement SME2 BFMLA, BFMLS [44/61] target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB [45/61] target/arm: Remove CPUARMState.vfp.scratch [46/61] target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN [47/61] target/arm: Implement SME2 FCVT (widening), FCVTL [48/61] target/arm: Implement SME2 FCVTZS, FCVTZU [49/61] target/arm: Implement SME2 SCVTF, UCVTF [50/61] target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA [51/61] target/arm: Introduce do_[us]sat_[bhs] macros [52/61] target/arm: Use do_[us]sat_[bhs] in sve_helper.c [53/61] target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU [54/61] target/arm: Implement SME2 SUNPK, UUNPK [55/61] target/arm: Implement SME2 ZIP, UZP (four registers) [56/61] target/arm: Move do_urshr, do_srshr to vec_internal.h [57/61] target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN [58/61] target/arm: Implement SME2 ZIP, UZP (two registers) [59/61] target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP [60/61] target/arm: Implement SME2 SEL [61/61] target/arm: Enable FEAT_SME2, FEAT_SME_F16F16, FEAT_SVE_B16B16 on -cpu max

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20250206195715.2150758-49-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 48/61] target/arm: Implement SME2 FCVTZS, FCVTZU
Date: Thu,  6 Feb 2025 11:57:02 -0800
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Series

target/arm: Implement FEAT_SME2 | expand

Commit Message

Richard Henderson Feb. 6, 2025, 7:57 p.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate-sme.c | 5 +++++
 target/arm/tcg/sme.decode      | 9 +++++++++
 2 files changed, 14 insertions(+)

diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 2b45244e23..4b45459e77 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -1293,3 +1293,8 @@  TRANS_FEAT(FCVT_w, aa64_sme2_f16f16, do_zz_fpst, a, 0,
            FPST_A64_F16, gen_helper_sme2_fcvt_w)
 TRANS_FEAT(FCVTL, aa64_sme2_f16f16, do_zz_fpst, a, 0,
            FPST_A64_F16, gen_helper_sme2_fcvtl)
+
+TRANS_FEAT(FCVTZS, aa64_sme2, do_zz_fpst, a, 0,
+           FPST_A64, gen_helper_gvec_vcvt_rz_fs)
+TRANS_FEAT(FCVTZU, aa64_sme2, do_zz_fpst, a, 0,
+           FPST_A64, gen_helper_gvec_vcvt_rz_fu)
diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode
index 644794bdc1..bb985f6f61 100644
--- a/target/arm/tcg/sme.decode
+++ b/target/arm/tcg/sme.decode
@@ -727,6 +727,10 @@  FMLS_nx_d       11000001 1101 .... 1 .. 00. ...00 10 ...    @azx_4x1_i1_o3
                 &zz_n n=1 zn=%zn_ax2
 @zz_2x1         ........ ... ..... ...... zn:5  .....       \
                 &zz_n n=1 zd=%zd_ax2
+@zz_2x2         ........ ... ..... ...... .... . .....      \
+                &zz_n n=2 zd=%zd_ax2 zn=%zn_ax2
+@zz_4x4         ........ ... ..... ...... .... . .....      \
+                &zz_n n=4 zd=%zd_ax4 zn=%zn_ax4
 
 BFCVT           11000001 011 00000 111000 ....0 .....       @zz_1x2
 BFCVTN          11000001 011 00000 111000 ....1 .....       @zz_1x2
@@ -736,3 +740,8 @@  FCVTN           11000001 001 00000 111000 ....1 .....       @zz_1x2
 
 FCVT_w          11000001 101 00000 111000 ..... ....0       @zz_2x1
 FCVTL           11000001 101 00000 111000 ..... ....1       @zz_2x1
+
+FCVTZS          11000001 001 00001 111000 ....0 ....0       @zz_2x2
+FCVTZS          11000001 001 10001 111000 ...00 ...00       @zz_4x4
+FCVTZU          11000001 001 00001 111000 ....1 ....0       @zz_2x2
+FCVTZU          11000001 001 10001 111000 ...01 ...00       @zz_4x4

[48/61] target/arm: Implement SME2 FCVTZS, FCVTZU

Commit Message

Patch