| Message ID | 20250206-qcs8300-pcie-smmu-v1-1-8eee0e3585bc@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: qcs8300: add the pcie smmu node | expand |
Hi Everyone Requesting your kind attention on this patch. I would highly welcome any feedback on this and truly appreciate your time and consideration.
On Thu, Feb 06, 2025 at 07:13:17PM +0530, Pratyush Brahma wrote: > Add the PCIe SMMU node to enable address translations > for pcie. > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> Though I see a little benefit in having this SMMU node if it is not followed by the PCIe enablement.
On 3/12/2025 12:23 PM, Dmitry Baryshkov wrote: > On Thu, Feb 06, 2025 at 07:13:17PM +0530, Pratyush Brahma wrote: >> Add the PCIe SMMU node to enable address translations >> for pcie. >> >> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 75 insertions(+) >> > Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> > > Though I see a little benefit in having this SMMU node if it is not > followed by the PCIe enablement. Thanks for the review! PCIe enablement changes for qcs8300 have been posted already [1] and [1] needs this patch as mentioned in [2]. [1] https://lore.kernel.org/lkml/20250310063103.3924525-8-quic_ziyuzhan@quicinc.com [2] https://lore.kernel.org/lkml/20250310063103.3924525-1-quic_ziyuzhan@quicinc.com
On Wed, Mar 12, 2025 at 12:41:38PM +0530, Pratyush Brahma wrote: > > On 3/12/2025 12:23 PM, Dmitry Baryshkov wrote: > > On Thu, Feb 06, 2025 at 07:13:17PM +0530, Pratyush Brahma wrote: > > > Add the PCIe SMMU node to enable address translations > > > for pcie. > > > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > > > --- > > > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ > > > 1 file changed, 75 insertions(+) > > > > > Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> > > > > Though I see a little benefit in having this SMMU node if it is not > > followed by the PCIe enablement. > > Thanks for the review! > > PCIe enablement changes for qcs8300 have been posted already [1] and [1] > needs > this patch as mentioned in [2]. Ack. In future please consider posting series in a logical way: if PCIe SMMU is only useful for PCIe and it is required for PCIe to work it makes much more sense to have it as a part of the PCIe enablement series rather than having it as a separate patch which can easily get lost. > > [1] https://lore.kernel.org/lkml/20250310063103.3924525-8-quic_ziyuzhan@quicinc.com > [2] https://lore.kernel.org/lkml/20250310063103.3924525-1-quic_ziyuzhan@quicinc.com > > -- > Thanks and Regards > Pratyush Brahma >
On 3/12/2025 2:14 PM, Dmitry Baryshkov wrote: > On Wed, Mar 12, 2025 at 12:41:38PM +0530, Pratyush Brahma wrote: >> On 3/12/2025 12:23 PM, Dmitry Baryshkov wrote: >>> On Thu, Feb 06, 2025 at 07:13:17PM +0530, Pratyush Brahma wrote: >>>> Add the PCIe SMMU node to enable address translations >>>> for pcie. >>>> >>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ >>>> 1 file changed, 75 insertions(+) >>>> >>> Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> >>> >>> Though I see a little benefit in having this SMMU node if it is not >>> followed by the PCIe enablement. >> Thanks for the review! >> >> PCIe enablement changes for qcs8300 have been posted already [1] and [1] >> needs >> this patch as mentioned in [2]. > Ack. In future please consider posting series in a logical way: if PCIe > SMMU is only useful for PCIe and it is required for PCIe to work it > makes much more sense to have it as a part of the PCIe enablement series > rather than having it as a separate patch which can easily get lost. Sure, will keep this in mind further. > >> [1] https://lore.kernel.org/lkml/20250310063103.3924525-8-quic_ziyuzhan@quicinc.com >> [2] https://lore.kernel.org/lkml/20250310063103.3924525-1-quic_ziyuzhan@quicinc.com >> >> -- >> Thanks and Regards >> Pratyush Brahma >>
On 3/12/25 7:53 AM, Dmitry Baryshkov wrote: > On Thu, Feb 06, 2025 at 07:13:17PM +0530, Pratyush Brahma wrote: >> Add the PCIe SMMU node to enable address translations >> for pcie. >> >> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 75 insertions(+) >> > > Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> Please hold off merging this patch, there's some internal investigation required Konrad
Hi Konrad Can you please share any updates from your internal investigation? Do you still have concerns or can this be merged?
Hi Bjorn Can this be considered for merge given that no concerns have been raised in the past few weeks?
On 3/28/25 9:51 AM, Pratyush Brahma wrote: > Hi Konrad > > Can you please share any updates from your internal investigation? > Do you still have concerns or can this be merged? Pratyush, please check the internal e-mail thread. Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..fe88244771583de9fed7b7e88c69a14872d4ffc8 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -3199,6 +3199,81 @@ apps_smmu: iommu@15000000 { <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>,
Add the PCIe SMMU node to enable address translations for pcie. Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) --- base-commit: a13f6e0f405ed0d3bcfd37c692c7d7fa3c052154 change-id: 20250206-qcs8300-pcie-smmu-4c8121c739e8 Best regards,