diff mbox series

ARM: dts: qcom: msm8960: Add BAM

Message ID 20250208-expressatt-bam-v1-1-8794ec853442@gmail.com
State New
Headers show
Series ARM: dts: qcom: msm8960: Add BAM | expand

Commit Message

Rudraksha Gupta Feb. 8, 2025, 7:21 p.m. UTC 
Copy bam nodes from qcom-ipq8064.dtsi and change
the regulator values to match msm8960.

Signed-off-by: Rudraksha Gupta <guptarud@gmail.com>
Co-developed-by: Sam Day <me@samcday.com>
Signed-off-by: Sam Day <me@samcday.com>
---
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)


---
base-commit: ffd294d346d185b70e28b1a28abe367bbfe53c04
change-id: 20250208-expressatt-bam-d0ed9863a626

Best regards,

Comments

Rudraksha Gupta Feb. 9, 2025, 11:54 p.m. UTC | #1 
> > +             sdcc3bam: dma-controller@12182000 {
> > +                     compatible = "qcom,bam-v1.3.0";
> > +                     reg = <0x12182000 0x2000>;
>
> APQ8064 has 0x8000 here, but I think 0x2000 should be enough.

Downstream seems to use 0x2000:
https://codeberg.org/LogicalErzor/Android_Kernel_Samsung_D2/src/branch/cm-14.1/arch/arm/mach-msm/devices-8960.c#L1217

>
> > +                     interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&gcc SDC3_H_CLK>;
> > +                     clock-names = "bam_clk";
> > +                     #dma-cells = <1>;
> > +                     qcom,ee = <0>;
> > +             };
>
> Please keep DT nodes sorted on the @reg part. So sdcc3bam goes after
> sdcc3 node, sdcc1bam goes after sdcc1.


Thanks! I've sent in v2.
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 865fe7cc39511d7cb9ec5c4b12100404f77e2989..01eed68c8f89b547ff0c173b2ca85a54efa29b7f 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -275,11 +275,31 @@  rng@1a500000 {
 			clock-names = "core";
 		};
 
+		sdcc3bam: dma-controller@12182000 {
+			compatible = "qcom,bam-v1.3.0";
+			reg = <0x12182000 0x2000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc SDC3_H_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
+		sdcc1bam: dma-controller@12402000 {
+			compatible = "qcom,bam-v1.3.0";
+			reg = <0x12402000 0x2000>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc SDC1_H_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
 		sdcc3: mmc@12180000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x00051180>;
 			status = "disabled";
-			reg = <0x12180000 0x8000>;
+			reg = <0x12180000 0x2000>;
 			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 			clock-names = "mclk", "apb_pclk";
@@ -289,13 +309,15 @@  sdcc3: mmc@12180000 {
 			max-frequency = <192000000>;
 			no-1-8-v;
 			vmmc-supply = <&vsdcc_fixed>;
+			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+			dma-names = "tx", "rx";
 		};
 
 		sdcc1: mmc@12400000 {
 			status = "disabled";
 			compatible = "arm,pl18x", "arm,primecell";
 			arm,primecell-periphid = <0x00051180>;
-			reg = <0x12400000 0x8000>;
+			reg = <0x12400000 0x2000>;
 			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 			clock-names = "mclk", "apb_pclk";
@@ -305,6 +327,8 @@  sdcc1: mmc@12400000 {
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			vmmc-supply = <&vsdcc_fixed>;
+			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+			dma-names = "tx", "rx";
 		};
 
 		tcsr: syscon@1a400000 {