@@ -79,6 +79,7 @@ extern unsigned int __ro_after_init kvm_host_max_vl[ARM64_VEC_MAX];
DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
int __init kvm_arm_init_sve(void);
+int __init kvm_arm_init_sme(void);
u32 __attribute_const__ kvm_target_cpu(void);
void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
@@ -1013,10 +1014,10 @@ struct kvm_vcpu_arch {
size_t __size_ret; \
unsigned int __vcpu_vq; \
\
- if (WARN_ON(!sve_vl_valid((vcpu)->arch.max_vl[ARM64_VEC_SVE]))) { \
+ if (WARN_ON(!sve_vl_valid(vcpu_max_vl(vcpu)))) { \
__size_ret = 0; \
} else { \
- __vcpu_vq = vcpu_sve_max_vq(vcpu); \
+ __vcpu_vq = sve_vl_from_vq(vcpu_max_vl(vcpu)); \
__size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
} \
\
@@ -105,6 +105,7 @@ struct kvm_regs {
#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */
+#define KVM_ARM_VCPU_SME 8 /* enable SME for this CPU */
/*
* An alias for _SVE since we finalize VL configuration for both SVE and SME
@@ -377,6 +377,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
case KVM_CAP_ARM_SVE:
r = system_supports_sve();
break;
+ case KVM_CAP_ARM_SME:
+ r = system_supports_sme();
+ break;
case KVM_CAP_ARM_PTRAUTH_ADDRESS:
case KVM_CAP_ARM_PTRAUTH_GENERIC:
r = kvm_has_full_ptr_auth();
@@ -1394,6 +1397,9 @@ static unsigned long system_supported_vcpu_features(void)
if (!system_supports_sve())
clear_bit(KVM_ARM_VCPU_SVE, &features);
+ if (!system_supports_sme())
+ clear_bit(KVM_ARM_VCPU_SME, &features);
+
if (!kvm_has_full_ptr_auth()) {
clear_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, &features);
clear_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features);
@@ -2784,6 +2790,10 @@ static __init int kvm_arm_init(void)
if (err)
return err;
+ err = kvm_arm_init_sme();
+ if (err)
+ return err;
+
err = kvm_arm_vmid_alloc_init();
if (err) {
kvm_err("Failed to initialize VMID allocator.\n");
@@ -76,6 +76,34 @@ int __init kvm_arm_init_sve(void)
return 0;
}
+int __init kvm_arm_init_sme(void)
+{
+ if (system_supports_sme()) {
+ kvm_max_vl[ARM64_VEC_SME] = sme_max_virtualisable_vl();
+ kvm_host_max_vl[ARM64_VEC_SME] = sme_max_vl();
+ kvm_nvhe_sym(kvm_host_max_vl[ARM64_VEC_SME]) = kvm_host_max_vl[ARM64_VEC_SME];
+
+ /*
+ * The get_sve_reg()/set_sve_reg() ioctl interface will need
+ * to be extended with multiple register slice support in
+ * order to support vector lengths greater than
+ * VL_ARCH_MAX:
+ */
+ if (WARN_ON(kvm_max_vl[ARM64_VEC_SME] > VL_ARCH_MAX))
+ kvm_max_vl[ARM64_VEC_SME] = VL_ARCH_MAX;
+
+ /*
+ * Don't even try to make use of vector lengths that
+ * aren't available on all CPUs, for now:
+ */
+ if (kvm_max_vl[ARM64_VEC_SME] < sme_max_vl())
+ pr_warn("KVM: SME vector length for guests limited to %u bytes\n",
+ kvm_max_vl[ARM64_VEC_SME]);
+ }
+
+ return 0;
+}
+
static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
{
vcpu->arch.max_vl[ARM64_VEC_SVE] = kvm_max_vl[ARM64_VEC_SVE];
@@ -88,42 +116,84 @@ static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
set_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &vcpu->kvm->arch.flags);
}
+static void kvm_vcpu_enable_sme(struct kvm_vcpu *vcpu)
+{
+ vcpu->arch.max_vl[ARM64_VEC_SME] = kvm_max_vl[ARM64_VEC_SME];
+
+ /*
+ * Userspace can still customize the vector lengths by writing
+ * KVM_REG_ARM64_SME_VLS. Allocation is deferred until
+ * kvm_arm_vcpu_finalize(), which freezes the configuration.
+ */
+ set_bit(KVM_ARCH_FLAG_GUEST_HAS_SME, &vcpu->kvm->arch.flags);
+}
+
/*
- * Finalize vcpu's maximum SVE vector length, allocating
- * vcpu->arch.sve_state as necessary.
+ * Finalize vcpu's maximum vector lengths, allocating
+ * vcpu->arch.sve_state and vcpu->arch.sme_state as necessary.
*/
static int kvm_vcpu_finalize_vec(struct kvm_vcpu *vcpu)
{
- void *buf;
+ void *sve_state, *sme_state;
unsigned int vl;
- size_t reg_sz;
int ret;
- vl = vcpu->arch.max_vl[ARM64_VEC_SVE];
-
/*
* Responsibility for these properties is shared between
* kvm_arm_init_sve(), kvm_vcpu_enable_sve() and
* set_sve_vls(). Double-check here just to be sure:
*/
- if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() ||
- vl > VL_ARCH_MAX))
- return -EIO;
+ if (vcpu_has_sve(vcpu)) {
+ vl = vcpu->arch.max_vl[ARM64_VEC_SVE];
+ if (WARN_ON(!sve_vl_valid(vl) ||
+ vl > sve_max_virtualisable_vl() ||
+ vl > VL_ARCH_MAX))
+ return -EIO;
+ }
- reg_sz = vcpu_sve_state_size(vcpu);
- buf = kzalloc(reg_sz, GFP_KERNEL_ACCOUNT);
- if (!buf)
+ /* Similarly for SME */
+ if (vcpu_has_sme(vcpu)) {
+ vl = vcpu->arch.max_vl[ARM64_VEC_SME];
+ if (WARN_ON(!sve_vl_valid(vl) ||
+ vl > sme_max_virtualisable_vl() ||
+ vl > VL_ARCH_MAX))
+ return -EIO;
+ }
+
+ sve_state = kzalloc(vcpu_sve_state_size(vcpu), GFP_KERNEL_ACCOUNT);
+ if (!sve_state)
return -ENOMEM;
- ret = kvm_share_hyp(buf, buf + reg_sz);
- if (ret) {
- kfree(buf);
- return ret;
+ ret = kvm_share_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu));
+ if (ret)
+ goto err_sve_alloc;
+
+ if (vcpu_has_sme(vcpu)) {
+ sme_state = kzalloc(vcpu_sme_state_size(vcpu),
+ GFP_KERNEL_ACCOUNT);
+ if (!sme_state) {
+ ret = -ENOMEM;
+ goto err_sve_map;
+ }
+
+ ret = kvm_share_hyp(sme_state,
+ sme_state + vcpu_sme_state_size(vcpu));
+ if (ret)
+ goto err_sve_map;
+ } else {
+ sme_state = NULL;
}
-
- vcpu->arch.sve_state = buf;
+
+ vcpu->arch.sve_state = sve_state;
+ vcpu->arch.sme_state = sme_state;
vcpu_set_flag(vcpu, VCPU_VEC_FINALIZED);
return 0;
+
+err_sve_map:
+ kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu));
+err_sve_alloc:
+ kfree(sve_state);
+ return ret;
}
int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
@@ -153,11 +223,15 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu)
{
void *sve_state = vcpu->arch.sve_state;
+ void *sme_state = vcpu->arch.sme_state;
kvm_unshare_hyp(vcpu, vcpu + 1);
if (sve_state)
kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu));
kfree(sve_state);
+ if (sme_state)
+ kvm_unshare_hyp(sme_state, sme_state + vcpu_sme_state_size(vcpu));
+ kfree(sme_state);
kfree(vcpu->arch.ccsidr);
}
@@ -165,6 +239,8 @@ static void kvm_vcpu_reset_vec(struct kvm_vcpu *vcpu)
{
if (vcpu_has_sve(vcpu))
memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu));
+ if (vcpu_has_sme(vcpu))
+ memset(vcpu->arch.sme_state, 0, vcpu_sme_state_size(vcpu));
}
/**
@@ -207,6 +283,8 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu)
if (!kvm_arm_vcpu_vec_finalized(vcpu)) {
if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE))
kvm_vcpu_enable_sve(vcpu);
+ if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SME))
+ kvm_vcpu_enable_sme(vcpu);
} else {
kvm_vcpu_reset_vec(vcpu);
}
@@ -929,6 +929,7 @@ struct kvm_enable_cap {
#define KVM_CAP_PRE_FAULT_MEMORY 236
#define KVM_CAP_X86_APIC_BUS_CYCLES_NS 237
#define KVM_CAP_X86_GUEST_MODE 238
+#define KVM_CAP_ARM_SME 239
struct kvm_irq_routing_irqchip {
__u32 irqchip;
Since SME requires configuration of a vector length in order to know the size of both the streaming mode SVE state and ZA array we implement a capability for it and require that it be enabled and finalized before the SME specific state can be accessed, similarly to SVE. Due to the overlap with sizing the SVE state we finalise both SVE and SME with a single finalization, preventing any further changes to the SVE and SME configuration once KVM_ARM_VCPU_VEC (an alias for _VCPU_SVE) has been finalised. This is not a thing of great elegance but it ensures that we never have a state where one of SVE or SME is finalised and the other not, avoiding complexity. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/include/asm/kvm_host.h | 5 +- arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/arm.c | 10 ++++ arch/arm64/kvm/reset.c | 114 ++++++++++++++++++++++++++++++++------ include/uapi/linux/kvm.h | 1 + 5 files changed, 111 insertions(+), 20 deletions(-)