@@ -58,6 +58,7 @@ DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(rems, 1, 2, 0, TCG_OPF_INT)
DEF(remu, 1, 2, 0, TCG_OPF_INT)
+DEF(sar, 1, 2, 0, TCG_OPF_INT)
DEF(shl, 1, 2, 0, TCG_OPF_INT)
DEF(shr, 1, 2, 0, TCG_OPF_INT)
DEF(sub, 1, 2, 0, TCG_OPF_INT)
@@ -76,7 +77,6 @@ DEF(st8_i32, 0, 2, 1, 0)
DEF(st16_i32, 0, 2, 1, 0)
DEF(st_i32, 0, 2, 1, 0)
/* shifts/rotates */
-DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, 0)
DEF(rotr_i32, 1, 2, 0, 0)
DEF(deposit_i32, 1, 2, 2, 0)
@@ -115,7 +115,6 @@ DEF(st16_i64, 0, 2, 1, 0)
DEF(st32_i64, 0, 2, 1, 0)
DEF(st_i64, 0, 2, 1, 0)
/* shifts/rotates */
-DEF(sar_i64, 1, 2, 0, 0)
DEF(rotl_i64, 1, 2, 0, 0)
DEF(rotr_i64, 1, 2, 0, 0)
DEF(deposit_i64, 1, 2, 2, 0)
@@ -446,10 +446,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
}
return (uint64_t)x >> (y & 63);
- case INDEX_op_sar_i32:
- return (int32_t)x >> (y & 31);
-
- case INDEX_op_sar_i64:
+ case INDEX_op_sar:
+ if (type == TCG_TYPE_I32) {
+ return (int32_t)x >> (y & 31);
+ }
return (int64_t)x >> (y & 63);
case INDEX_op_rotr_i32:
@@ -2588,7 +2588,7 @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
}
switch (op->opc) {
- CASE_OP_32_64(sar):
+ case INDEX_op_sar:
/*
* Arithmetic right shift will not reduce the number of
* input sign repetitions.
@@ -3015,7 +3015,7 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(rotl):
CASE_OP_32_64(rotr):
- CASE_OP_32_64(sar):
+ case INDEX_op_sar:
case INDEX_op_shl:
case INDEX_op_shr:
done = fold_shift(&ctx, op);
@@ -511,7 +511,7 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
+ tcg_gen_op3_i32(INDEX_op_sar, ret, arg1, arg2);
}
void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
@@ -1624,7 +1624,7 @@ void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_REG_BITS == 64) {
- tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
+ tcg_gen_op3_i64(INDEX_op_sar, ret, arg1, arg2);
} else {
gen_helper_sar_i64(ret, arg1, arg2);
}
@@ -1042,8 +1042,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
- OUTOP(INDEX_op_sar_i32, TCGOutOpBinary, outop_sar),
- OUTOP(INDEX_op_sar_i64, TCGOutOpBinary, outop_sar),
+ OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar),
OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
@@ -5415,8 +5414,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_orc:
case INDEX_op_rems:
case INDEX_op_remu:
- case INDEX_op_sar_i32:
- case INDEX_op_sar_i64:
+ case INDEX_op_sar:
case INDEX_op_shl:
case INDEX_op_shr:
case INDEX_op_xor:
@@ -625,9 +625,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] >> (regs[r2] % TCG_TARGET_REG_BITS);
break;
- case INDEX_op_sar_i32:
+ case INDEX_op_sar:
tci_args_rrr(insn, &r0, &r1, &r2);
- regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
+ regs[r0] = ((tcg_target_long)regs[r1]
+ >> (regs[r2] % TCG_TARGET_REG_BITS));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
@@ -787,10 +788,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Shift/rotate operations (64 bit). */
- case INDEX_op_sar_i64:
- tci_args_rrr(insn, &r0, &r1, &r2);
- regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
- break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
@@ -1073,12 +1070,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_orc:
case INDEX_op_rems:
case INDEX_op_remu:
+ case INDEX_op_sar:
case INDEX_op_shl:
case INDEX_op_shr:
case INDEX_op_sub:
case INDEX_op_xor:
- case INDEX_op_sar_i32:
- case INDEX_op_sar_i64:
case INDEX_op_rotl_i32:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
@@ -389,10 +389,10 @@ Shifts/Rotates
- | *t0* = *t1* >> *t2* (unsigned)
| Unspecified behavior for negative or out-of-range shifts.
- * - sar_i32/i64 *t0*, *t1*, *t2*
+ * - sar *t0*, *t1*, *t2*
- | *t0* = *t1* >> *t2* (signed)
- | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
+ | Unspecified behavior for negative or out-of-range shifts.
* - rotl_i32/i64 *t0*, *t1*, *t2*
@@ -779,7 +779,7 @@ static void tgen_sar(TCGContext *s, TCGType type,
tcg_out_ext32s(s, TCG_REG_TMP, a1);
a1 = TCG_REG_TMP;
}
- tcg_out_op_rrr(s, glue(INDEX_op_sar_i,TCG_TARGET_REG_BITS), a0, a1, a2);
+ tcg_out_op_rrr(s, INDEX_op_sar, a0, a1, a2);
}
static const TCGOutOpBinary outop_sar = {
@@ -897,7 +897,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, opc, args[0], args[1], args[2]);
break;
- CASE_32_64(sar)
CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */
CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */
CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/tcg/tcg-opc.h | 3 +-- tcg/optimize.c | 12 ++++++------ tcg/tcg-op.c | 4 ++-- tcg/tcg.c | 6 ++---- tcg/tci.c | 12 ++++-------- docs/devel/tcg-ops.rst | 4 ++-- tcg/tci/tcg-target.c.inc | 3 +-- 7 files changed, 18 insertions(+), 26 deletions(-)