| Message ID | 20250217193453.2874125-1-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Tue, Feb 18, 2025 at 3:35 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > v2: Fix target/loongarch printf formats for vaddr > Include two more reviewed patches. > > This time with actual pull urls. :-/ > > r~ > > > The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec: > > Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2 > > for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb: > > tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800) There is still a macOS build failure: https://gitlab.com/qemu-project/qemu/-/jobs/9165757871#L5509 ../target/mips/tcg/octeon_translate.c:22:39: error: format specifies type 'unsigned long long' but the argument has type 'vaddr' (aka 'unsigned long') [-Werror,-Wformat] 21 | LOG_DISAS("Branch in delay / forbidden slot at PC 0x" | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 | TARGET_FMT_lx "\n", ctx->base.pc_next); | ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ ../target/mips/tcg/translate.h:197:49: note: expanded from macro 'LOG_DISAS' 197 | qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~ /private/var/folders/xf/_tm0f94d66n8kr12tqwrylrr0000gn/T/cirrus-ci-build/include/qemu/log.h:57:30: note: expanded from macro 'qemu_log_mask' 57 | qemu_log(FMT, ## __VA_ARGS__); \ | ~~~ ^~~~~~~~~~~ Stefan > > ---------------------------------------------------------------- > tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS > tcg: Cleanups after disallowing 64-on-32 > tcg: Introduce constraint for zero register > tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 > tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 > linux-user: Move TARGET_SA_RESTORER out of generic/signal.h > linux-user: Fix alignment when unmapping excess reservation > target/sparc: Fix register selection for all F*TOx and FxTO* instructions > target/sparc: Fix gdbstub incorrectly handling registers f32-f62 > target/sparc: fake UltraSPARC T1 PCR and PIC registers > > ---------------------------------------------------------------- > Andreas Schwab (1): > linux-user: Move TARGET_SA_RESTORER out of generic/signal.h > > Artyom Tarasenko (1): > target/sparc: fake UltraSPARC T1 PCR and PIC registers > > Fabiano Rosas (1): > elfload: Fix alignment when unmapping excess reservation > > Mikael Szreder (2): > target/sparc: Fix register selection for all F*TOx and FxTO* instructions > target/sparc: Fix gdbstub incorrectly handling registers f32-f62 > > Richard Henderson (22): > tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS > tcg: Remove TCG_OVERSIZED_GUEST > tcg: Drop support for two address registers in gen_ldst > tcg: Merge INDEX_op_qemu_*_{a32,a64}_* > tcg/arm: Drop addrhi from prepare_host_addr > tcg/i386: Drop addrhi from prepare_host_addr > tcg/mips: Drop addrhi from prepare_host_addr > tcg/ppc: Drop addrhi from prepare_host_addr > tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst > plugins: Fix qemu_plugin_read_memory_vaddr parameters > accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page > target/loongarch: Use VADDR_PRIx for logging pc_next > include/exec: Change vaddr to uintptr_t > include/exec: Use uintptr_t in CPUTLBEntry > tcg: Introduce the 'z' constraint for a hardware zero register > tcg/aarch64: Use 'z' constraint > tcg/loongarch64: Use 'z' constraint > tcg/mips: Use 'z' constraint > tcg/riscv: Use 'z' constraint > tcg/sparc64: Use 'z' constraint > tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 > tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 > > include/exec/tlb-common.h | 10 +- > include/exec/vaddr.h | 16 +- > include/qemu/atomic.h | 18 +- > include/tcg/oversized-guest.h | 23 --- > include/tcg/tcg-opc.h | 28 +-- > include/tcg/tcg.h | 3 +- > linux-user/aarch64/target_signal.h | 2 + > linux-user/arm/target_signal.h | 2 + > linux-user/generic/signal.h | 1 - > linux-user/i386/target_signal.h | 2 + > linux-user/m68k/target_signal.h | 1 + > linux-user/microblaze/target_signal.h | 2 + > linux-user/ppc/target_signal.h | 2 + > linux-user/s390x/target_signal.h | 2 + > linux-user/sh4/target_signal.h | 2 + > linux-user/x86_64/target_signal.h | 2 + > linux-user/xtensa/target_signal.h | 2 + > tcg/aarch64/tcg-target-con-set.h | 12 +- > tcg/aarch64/tcg-target.h | 2 + > tcg/loongarch64/tcg-target-con-set.h | 15 +- > tcg/loongarch64/tcg-target-con-str.h | 1 - > tcg/loongarch64/tcg-target-has.h | 2 - > tcg/loongarch64/tcg-target.h | 2 + > tcg/mips/tcg-target-con-set.h | 26 +-- > tcg/mips/tcg-target-con-str.h | 1 - > tcg/mips/tcg-target.h | 2 + > tcg/riscv/tcg-target-con-set.h | 10 +- > tcg/riscv/tcg-target-con-str.h | 1 - > tcg/riscv/tcg-target-has.h | 2 - > tcg/riscv/tcg-target.h | 2 + > tcg/sparc64/tcg-target-con-set.h | 12 +- > tcg/sparc64/tcg-target-con-str.h | 1 - > tcg/sparc64/tcg-target.h | 3 +- > tcg/tci/tcg-target.h | 1 - > accel/tcg/cputlb.c | 32 +--- > accel/tcg/tcg-all.c | 9 +- > linux-user/elfload.c | 4 +- > plugins/api.c | 2 +- > target/arm/ptw.c | 34 ---- > target/loongarch/tcg/translate.c | 2 +- > target/riscv/cpu_helper.c | 13 +- > target/sparc/gdbstub.c | 18 +- > target/sparc/translate.c | 19 +++ > tcg/optimize.c | 21 +-- > tcg/tcg-op-ldst.c | 103 +++-------- > tcg/tcg.c | 97 +++++------ > tcg/tci.c | 119 +++---------- > docs/devel/multi-thread-tcg.rst | 1 - > docs/devel/tcg-ops.rst | 4 +- > target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- > target/sparc/insns.decode | 19 ++- > tcg/aarch64/tcg-target.c.inc | 86 ++++------ > tcg/arm/tcg-target.c.inc | 114 ++++--------- > tcg/i386/tcg-target.c.inc | 190 +++++---------------- > tcg/loongarch64/tcg-target.c.inc | 72 +++----- > tcg/mips/tcg-target.c.inc | 169 ++++++------------ > tcg/ppc/tcg-target.c.inc | 164 +++++------------- > tcg/riscv/tcg-target.c.inc | 56 +++--- > tcg/s390x/tcg-target.c.inc | 40 ++--- > tcg/sparc64/tcg-target.c.inc | 45 ++--- > tcg/tci/tcg-target.c.inc | 60 ++----- > 61 files changed, 548 insertions(+), 1160 deletions(-) > delete mode 100644 include/tcg/oversized-guest.h >
v2: Fix target/loongarch printf formats for vaddr Include two more reviewed patches. This time with actual pull urls. :-/ r~ The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec: Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2 for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb: tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800) ---------------------------------------------------------------- tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Cleanups after disallowing 64-on-32 tcg: Introduce constraint for zero register tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 linux-user: Move TARGET_SA_RESTORER out of generic/signal.h linux-user: Fix alignment when unmapping excess reservation target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: fake UltraSPARC T1 PCR and PIC registers ---------------------------------------------------------------- Andreas Schwab (1): linux-user: Move TARGET_SA_RESTORER out of generic/signal.h Artyom Tarasenko (1): target/sparc: fake UltraSPARC T1 PCR and PIC registers Fabiano Rosas (1): elfload: Fix alignment when unmapping excess reservation Mikael Szreder (2): target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 Richard Henderson (22): tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Remove TCG_OVERSIZED_GUEST tcg: Drop support for two address registers in gen_ldst tcg: Merge INDEX_op_qemu_*_{a32,a64}_* tcg/arm: Drop addrhi from prepare_host_addr tcg/i386: Drop addrhi from prepare_host_addr tcg/mips: Drop addrhi from prepare_host_addr tcg/ppc: Drop addrhi from prepare_host_addr tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst plugins: Fix qemu_plugin_read_memory_vaddr parameters accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page target/loongarch: Use VADDR_PRIx for logging pc_next include/exec: Change vaddr to uintptr_t include/exec: Use uintptr_t in CPUTLBEntry tcg: Introduce the 'z' constraint for a hardware zero register tcg/aarch64: Use 'z' constraint tcg/loongarch64: Use 'z' constraint tcg/mips: Use 'z' constraint tcg/riscv: Use 'z' constraint tcg/sparc64: Use 'z' constraint tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 include/exec/tlb-common.h | 10 +- include/exec/vaddr.h | 16 +- include/qemu/atomic.h | 18 +- include/tcg/oversized-guest.h | 23 --- include/tcg/tcg-opc.h | 28 +-- include/tcg/tcg.h | 3 +- linux-user/aarch64/target_signal.h | 2 + linux-user/arm/target_signal.h | 2 + linux-user/generic/signal.h | 1 - linux-user/i386/target_signal.h | 2 + linux-user/m68k/target_signal.h | 1 + linux-user/microblaze/target_signal.h | 2 + linux-user/ppc/target_signal.h | 2 + linux-user/s390x/target_signal.h | 2 + linux-user/sh4/target_signal.h | 2 + linux-user/x86_64/target_signal.h | 2 + linux-user/xtensa/target_signal.h | 2 + tcg/aarch64/tcg-target-con-set.h | 12 +- tcg/aarch64/tcg-target.h | 2 + tcg/loongarch64/tcg-target-con-set.h | 15 +- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/loongarch64/tcg-target.h | 2 + tcg/mips/tcg-target-con-set.h | 26 +-- tcg/mips/tcg-target-con-str.h | 1 - tcg/mips/tcg-target.h | 2 + tcg/riscv/tcg-target-con-set.h | 10 +- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target-has.h | 2 - tcg/riscv/tcg-target.h | 2 + tcg/sparc64/tcg-target-con-set.h | 12 +- tcg/sparc64/tcg-target-con-str.h | 1 - tcg/sparc64/tcg-target.h | 3 +- tcg/tci/tcg-target.h | 1 - accel/tcg/cputlb.c | 32 +--- accel/tcg/tcg-all.c | 9 +- linux-user/elfload.c | 4 +- plugins/api.c | 2 +- target/arm/ptw.c | 34 ---- target/loongarch/tcg/translate.c | 2 +- target/riscv/cpu_helper.c | 13 +- target/sparc/gdbstub.c | 18 +- target/sparc/translate.c | 19 +++ tcg/optimize.c | 21 +-- tcg/tcg-op-ldst.c | 103 +++-------- tcg/tcg.c | 97 +++++------ tcg/tci.c | 119 +++---------- docs/devel/multi-thread-tcg.rst | 1 - docs/devel/tcg-ops.rst | 4 +- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- target/sparc/insns.decode | 19 ++- tcg/aarch64/tcg-target.c.inc | 86 ++++------ tcg/arm/tcg-target.c.inc | 114 ++++--------- tcg/i386/tcg-target.c.inc | 190 +++++---------------- tcg/loongarch64/tcg-target.c.inc | 72 +++----- tcg/mips/tcg-target.c.inc | 169 ++++++------------ tcg/ppc/tcg-target.c.inc | 164 +++++------------- tcg/riscv/tcg-target.c.inc | 56 +++--- tcg/s390x/tcg-target.c.inc | 40 ++--- tcg/sparc64/tcg-target.c.inc | 45 ++--- tcg/tci/tcg-target.c.inc | 60 ++----- 61 files changed, 548 insertions(+), 1160 deletions(-) delete mode 100644 include/tcg/oversized-guest.h