| Message ID | 20250219080059.367045-5-patrice.chotard@foss.st.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add STM32MP25 SPI NOR support | expand |
On 2/19/25 09:00, patrice.chotard@foss.st.com wrote: > From: Patrice Chotard <patrice.chotard@foss.st.com> > > Octo Memory Manager driver (OMM) manages: > - the muxing between 2 OSPI busses and 2 output ports. > There are 4 possible muxing configurations: > - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 > output is on port 2 > - OSPI1 and OSPI2 are multiplexed over the same output port 1 > - swapped mode (no multiplexing), OSPI1 output is on port 2, > OSPI2 output is on port 1 > - OSPI1 and OSPI2 are multiplexed over the same output port 2 > - the split of the memory area shared between the 2 OSPI instances. > - chip select selection override. > - the time between 2 transactions in multiplexed mode. > - check firewall access. > > Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> > Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> > --- > drivers/memory/Kconfig | 17 ++ > drivers/memory/Makefile | 1 + > drivers/memory/stm32_omm.c | 522 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 540 insertions(+) > create mode 100644 drivers/memory/stm32_omm.c > > diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig > index c82d8d8a16ea..3a0703fbfee7 100644 > --- a/drivers/memory/Kconfig > +++ b/drivers/memory/Kconfig > @@ -225,6 +225,23 @@ config STM32_FMC2_EBI > devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on > SOCs containing the FMC2 External Bus Interface. > > +config STM32_OMM > + tristate "STM32 Octo Memory Manager" > + depends on SPI_STM32_OSPI || COMPILE_TEST > + help > + This driver manages the muxing between the 2 OSPI busses and > + the 2 output ports. There are 4 possible muxing configurations: > + - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 > + output is on port 2 > + - OSPI1 and OSPI2 are multiplexed over the same output port 1 > + - swapped mode (no multiplexing), OSPI1 output is on port 2, > + OSPI2 output is on port 1 > + - OSPI1 and OSPI2 are multiplexed over the same output port 2 > + It also manages : > + - the split of the memory area shared between the 2 OSPI instances. > + - chip select selection override. > + - the time between 2 transactions in multiplexed mode. > + > source "drivers/memory/samsung/Kconfig" > source "drivers/memory/tegra/Kconfig" > > diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile > index d2e6ca9abbe0..c1959661bf63 100644 > --- a/drivers/memory/Makefile > +++ b/drivers/memory/Makefile > @@ -24,6 +24,7 @@ obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o > obj-$(CONFIG_PL353_SMC) += pl353-smc.o > obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o > obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o > +obj-$(CONFIG_STM32_OMM) += stm32_omm.o > > obj-$(CONFIG_SAMSUNG_MC) += samsung/ > obj-$(CONFIG_TEGRA_MC) += tegra/ > diff --git a/drivers/memory/stm32_omm.c b/drivers/memory/stm32_omm.c > new file mode 100644 > index 000000000000..8f7f475769e7 > --- /dev/null > +++ b/drivers/memory/stm32_omm.c > @@ -0,0 +1,522 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved > + * Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroelectronics. > + */ > + > +#include <linux/bitfield.h> > +#include <linux/bus/stm32_firewall_device.h> > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/mfd/syscon.h> > +#include <linux/mod_devicetable.h> > +#include <linux/module.h> > +#include <linux/of_address.h> > +#include <linux/of_platform.h> > +#include <linux/pinctrl/consumer.h> > +#include <linux/pm_runtime.h> > +#include <linux/regmap.h> > +#include <linux/reset.h> > + > +#define OMM_CR 0 > +#define CR_MUXEN BIT(0) > +#define CR_MUXENMODE_MASK GENMASK(1, 0) > +#define CR_CSSEL_OVR_EN BIT(4) > +#define CR_CSSEL_OVR_MASK GENMASK(6, 5) > +#define CR_REQ2ACK_MASK GENMASK(23, 16) > + > +#define OMM_CHILD_NB 2 > + > +struct ospi_child { > + struct device *dev; > + struct device_node *node; > + struct clk *clk; > +}; > + > +struct stm32_omm { > + struct ospi_child child[OMM_CHILD_NB]; > + struct resource *mm_res; > + struct clk *clk; > + void __iomem *io_base; > + u32 cr; > + u8 nb_child; > + bool restore_omm; > +}; > + > +static int stm32_omm_set_amcr(struct device *dev, bool set) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + struct regmap *syscfg_regmap; > + struct device_node *node; > + struct resource res, res1; > + resource_size_t mm_ospi2_size = 0; > + static const char * const mm_name[] = { "ospi1", "ospi2" }; > + u32 amcr_base, amcr_mask; > + int ret, idx; > + unsigned int i, amcr, read_amcr; > + > + for (i = 0; i < omm->nb_child; i++) { > + idx = of_property_match_string(dev->of_node, > + "memory-region-names", > + mm_name[i]); > + if (idx < 0) > + continue; > + > + /* res1 only used on second loop iteration */ > + res1.start = res.start; > + res1.end = res.end; > + > + node = of_parse_phandle(dev->of_node, "memory-region", idx); > + if (!node) > + continue; > + > + ret = of_address_to_resource(node, 0, &res); > + if (ret) { > + dev_err(dev, "unable to resolve memory region\n"); > + return ret; > + } > + > + /* check that memory region fits inside OMM memory map area */ > + if (!resource_contains(omm->mm_res, &res)) { > + dev_err(dev, "%s doesn't fit inside OMM memory map area\n", > + mm_name[i]); > + dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res); > + > + return -EFAULT; > + } > + > + if (i == 1) { > + mm_ospi2_size = resource_size(&res); > + > + /* check that OMM memory region 1 doesn't overlap memory region 2 */ > + if (resource_overlaps(&res, &res1)) { > + dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", > + mm_name[0], mm_name[1]); > + dev_err(dev, "%pR overlaps %pR\n", &res1, &res); > + > + return -EFAULT; > + } > + } > + } > + > + syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr"); > + if (IS_ERR(syscfg_regmap)) { > + dev_err(dev, "Failed to get st,syscfg-amcr property\n"); > + return PTR_ERR(syscfg_regmap); > + } > + > + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1, > + &amcr_base); > + if (ret) > + return ret; > + > + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2, > + &amcr_mask); > + if (ret) > + return ret; > + > + amcr = mm_ospi2_size / SZ_64M; > + > + if (set) > + regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr); > + > + /* read AMCR and check coherency with memory-map areas defined in DT */ > + regmap_read(syscfg_regmap, amcr_base, &read_amcr); > + read_amcr = read_amcr >> (ffs(amcr_mask) - 1); > + > + if (amcr != read_amcr) { > + dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); > + ret = -EINVAL; > + } > + > + return ret; > +} > + > +static int stm32_omm_enable_child_clock(struct device *dev, bool enable) > +{ > + /* As there is only 2 children, remember first child in case of error */ > + struct clk *first_child_clk = NULL; > + struct stm32_omm *omm = dev_get_drvdata(dev); > + u8 i; > + int ret; > + > + for (i = 0; i < omm->nb_child; i++) { > + if (enable) { > + ret = clk_prepare_enable(omm->child[i].clk); > + if (ret) { > + if (first_child_clk) > + clk_disable_unprepare(first_child_clk); > + > + dev_err(dev, "Can not enable clock\n"); > + return ret; > + } > + } else { > + clk_disable_unprepare(omm->child[i].clk); > + } > + > + first_child_clk = omm->child[i].clk; > + } > + > + return 0; > +} > + > +static int stm32_omm_configure(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + struct reset_control *rstc; > + unsigned long clk_rate, clk_rate_max = 0; > + int ret; > + u8 i; > + u32 mux = 0; > + u32 cssel_ovr = 0; > + u32 req2ack = 0; > + > + omm->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(omm->clk)) { > + dev_err(dev, "Failed to get OMM clock (%ld)\n", > + PTR_ERR(omm->clk)); > + > + return PTR_ERR(omm->clk); > + } > + > + ret = pm_runtime_resume_and_get(dev); > + if (ret < 0) > + return ret; > + > + /* parse children's clock */ > + for (i = 0; i < omm->nb_child; i++) { > + clk_rate = clk_get_rate(omm->child[i].clk); > + if (!clk_rate) { > + dev_err(dev, "Invalid clock rate\n"); > + pm_runtime_disable(dev); > + goto err_clk_disable; > + } > + > + if (clk_rate > clk_rate_max) > + clk_rate_max = clk_rate; > + } > + > + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); > + if (IS_ERR(rstc)) { > + ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); > + pm_runtime_disable(dev); > + goto err_clk_disable; > + } > + > + reset_control_assert(rstc); > + udelay(2); > + reset_control_deassert(rstc); > + > + omm->cr = readl_relaxed(omm->io_base + OMM_CR); > + /* optional */ > + ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux); > + if (!ret) { > + if (mux & CR_MUXEN) { > + ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", > + &req2ack); > + if (!ret && !req2ack) { > + req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; > + > + if (req2ack > 256) > + req2ack = 256; > + } > + > + req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); > + > + omm->cr &= ~CR_REQ2ACK_MASK; > + omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack); > + > + /* > + * If the mux is enabled, the 2 OSPI clocks have to be > + * always enabled > + */ > + ret = stm32_omm_enable_child_clock(dev, true); > + if (ret) { > + pm_runtime_disable(dev); > + goto err_clk_disable; > + } > + } > + > + omm->cr &= ~CR_MUXENMODE_MASK; > + omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux); > + } > + > + /* optional */ > + ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr); > + if (!ret) { > + omm->cr &= ~CR_CSSEL_OVR_MASK; > + omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); > + omm->cr |= CR_CSSEL_OVR_EN; > + } > + > + omm->restore_omm = true; > + writel_relaxed(omm->cr, omm->io_base + OMM_CR); > + > + ret = stm32_omm_set_amcr(dev, true); > + > +err_clk_disable: > + pm_runtime_put_sync_suspend(dev); > + > + return ret; > +} > + > +static int stm32_omm_check_access(struct device *dev, struct device_node *np) > +{ > + struct stm32_firewall firewall; > + int ret; > + > + ret = stm32_firewall_get_firewall(np, &firewall, 1); > + if (ret) > + return ret; > + > + return stm32_firewall_grant_access(&firewall); > +} > + > +static int stm32_omm_disable_child(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + struct reset_control *reset; > + int ret; > + u8 i; > + > + for (i = 0; i < omm->nb_child; i++) { > + ret = clk_prepare_enable(omm->child[i].clk); > + if (ret) { > + dev_err(dev, "Can not enable clock\n"); > + return ret; > + } > + > + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); > + if (IS_ERR(reset)) { > + dev_err(dev, "Can't get child reset\n"); > + return PTR_ERR(reset); > + }; > + > + /* reset OSPI to ensure CR_EN bit is set to 0 */ > + reset_control_assert(reset); > + udelay(2); > + reset_control_deassert(reset); > + > + reset_control_put(reset); > + clk_disable_unprepare(omm->child[i].clk); > + } > + > + return 0; > +} > + > +static int stm32_omm_probe(struct platform_device *pdev) > +{ > + struct platform_device *vdev; > + struct device *dev = &pdev->dev; > + struct stm32_omm *omm; > + struct clk *clk; > + int ret; > + u8 child_access_granted = 0; > + u8 i, j; > + bool child_access[OMM_CHILD_NB]; > + > + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); > + if (!omm) > + return -ENOMEM; > + > + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); > + if (IS_ERR(omm->io_base)) > + return PTR_ERR(omm->io_base); > + > + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); > + if (IS_ERR(omm->mm_res)) > + return PTR_ERR(omm->mm_res); > + > + /* check child's access */ > + for_each_child_of_node_scoped(dev->of_node, child) { > + if (omm->nb_child >= OMM_CHILD_NB) { > + dev_err(dev, "Bad DT, found too much children\n"); > + ret = -E2BIG; > + goto err_clk_release; > + } > + > + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { > + ret = -EINVAL; > + goto err_clk_release; > + } > + > + ret = stm32_omm_check_access(dev, child); > + if (ret < 0 && ret != -EACCES) > + goto err_clk_release; > + > + child_access[omm->nb_child] = false; > + if (!ret) { > + child_access_granted++; > + child_access[omm->nb_child] = true; > + } > + > + omm->child[omm->nb_child].node = child; > + > + clk = of_clk_get(child, 0); > + if (IS_ERR(clk)) { > + dev_err(dev, "Can't get child clock\n"); > + ret = PTR_ERR(clk); > + goto err_clk_release; > + }; > + > + omm->child[omm->nb_child].clk = clk; > + omm->nb_child++; > + } > + > + if (omm->nb_child != OMM_CHILD_NB) { > + ret = -EINVAL; > + goto err_clk_release; > + } > + > + platform_set_drvdata(pdev, omm); > + > + pm_runtime_enable(dev); > + > + /* check if OMM's resource access is granted */ > + ret = stm32_omm_check_access(dev, dev->of_node); > + if (ret < 0 && ret != -EACCES) > + goto err_clk_release; > + > + if (!ret && child_access_granted == OMM_CHILD_NB) { > + /* Ensure both OSPI instance are disabled before configuring OMM */ > + ret = stm32_omm_disable_child(dev); > + if (ret) > + goto err_clk_release; > + > + ret = stm32_omm_configure(dev); > + if (ret) > + goto err_clk_release; > + } else { > + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); > + /* > + * AMCR can't be set, so check if current value is coherent > + * with memory-map areas defined in DT > + */ > + ret = stm32_omm_set_amcr(dev, false); > + if (ret) > + goto err_clk_release; > + } > + > + /* for each child, if resource access is granted and status "okay", probe it */ > + for (i = 0; i < omm->nb_child; i++) { > + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) > + continue; > + > + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); > + if (!vdev) { > + dev_err(dev, "Failed to create Octo Memory Manager child\n"); > + for (j = i; j > 0; --j) { > + if (omm->child[j].dev) > + of_platform_device_destroy(omm->child[j].dev, NULL); > + } > + > + ret = -EINVAL; > + goto err_clk_release; > + } > + omm->child[i].dev = &vdev->dev; > + } > + > +err_clk_release: > + for (i = 0; i < omm->nb_child; i++) > + clk_put(omm->child[i].clk); > + > + return ret; > +} > + > +static void stm32_omm_remove(struct platform_device *pdev) > +{ > + struct stm32_omm *omm = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < omm->nb_child; i++) > + if (omm->child[i].dev) > + of_platform_device_destroy(omm->child[i].dev, NULL); > + > + if (omm->cr & CR_MUXEN) > + stm32_omm_enable_child_clock(&pdev->dev, false); > + > + pm_runtime_disable(&pdev->dev); > +} > + > +static const struct of_device_id stm32_omm_of_match[] = { > + { .compatible = "st,stm32mp25-omm", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, stm32_omm_of_match); > + > +static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + > + clk_disable_unprepare(omm->clk); > + > + return 0; > +} > + > +static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + > + return clk_prepare_enable(omm->clk); > +} > + > +static int __maybe_unused stm32_omm_suspend(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + > + if (omm->restore_omm && omm->cr & CR_MUXEN) > + stm32_omm_enable_child_clock(dev, false); > + > + return pinctrl_pm_select_sleep_state(dev); > +} > + > +static int __maybe_unused stm32_omm_resume(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + int ret; > + > + pinctrl_pm_select_default_state(dev); > + > + if (!omm->restore_omm) > + return 0; > + > + /* Ensure both OSPI instance are disabled before configuring OMM */ > + ret = stm32_omm_disable_child(dev); > + if (ret) > + return ret; > + > + ret = pm_runtime_resume_and_get(dev); > + if (ret < 0) > + return ret; > + > + writel_relaxed(omm->cr, omm->io_base + OMM_CR); > + ret = stm32_omm_set_amcr(dev, true); > + pm_runtime_put_sync_suspend(dev); > + if (ret) > + return ret; > + > + if (omm->cr & CR_MUXEN) > + ret = stm32_omm_enable_child_clock(dev, true); > + > + return ret; > +} > + > +static const struct dev_pm_ops stm32_omm_pm_ops = { > + SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend, > + stm32_omm_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume) > +}; > + > +static struct platform_driver stm32_omm_driver = { > + .probe = stm32_omm_probe, > + .remove = stm32_omm_remove, > + .driver = { > + .name = "stm32-omm", > + .of_match_table = stm32_omm_of_match, > + .pm = &stm32_omm_pm_ops, > + }, > +}; > +module_platform_driver(stm32_omm_driver); > + > +MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver"); > +MODULE_LICENSE("GPL"); Hi all, Anybody alse has additionnal remarks on this driver ? Thanks Patrice
On 10/03/2025 14:52, Patrice CHOTARD wrote: > > > On 2/19/25 09:00, patrice.chotard@foss.st.com wrote: >> From: Patrice Chotard <patrice.chotard@foss.st.com> >> >> Octo Memory Manager driver (OMM) manages: >> - the muxing between 2 OSPI busses and 2 output ports. >> There are 4 possible muxing configurations: >> - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 >> output is on port 2 >> - OSPI1 and OSPI2 are multiplexed over the same output port 1 >> - swapped mode (no multiplexing), OSPI1 output is on port 2, >> OSPI2 output is on port 1 >> - OSPI1 and OSPI2 are multiplexed over the same output port 2 >> - the split of the memory area shared between the 2 OSPI instances. >> - chip select selection override. >> - the time between 2 transactions in multiplexed mode. >> - check firewall access. >> Please kindly trim the replies from unnecessary context. It makes it much easier to find new content. ... > > > Hi all, > > Anybody alse has additionnal remarks on this driver ? I am waiting too... Best regards, Krzysztof
On 19/02/2025 09:00, patrice.chotard@foss.st.com wrote: > From: Patrice Chotard <patrice.chotard@foss.st.com> > > Octo Memory Manager driver (OMM) manages: > - the muxing between 2 OSPI busses and 2 output ports. > There are 4 possible muxing configurations: > - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 > output is on port 2 > - OSPI1 and OSPI2 are multiplexed over the same output port 1 > - swapped mode (no multiplexing), OSPI1 output is on port 2, > OSPI2 output is on port 1 > - OSPI1 and OSPI2 are multiplexed over the same output port 2 > - the split of the memory area shared between the 2 OSPI instances. > - chip select selection override. > - the time between 2 transactions in multiplexed mode. > - check firewall access. > > Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> > Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Incorrect chain. You sent it, so you must be the last person signing it. I was waiting for any ST review... did not happen, so if you wonder how to speed things up, you got a hint. Anyway, many questions futher. > + > + if (i == 1) { > + mm_ospi2_size = resource_size(&res); > + > + /* check that OMM memory region 1 doesn't overlap memory region 2 */ > + if (resource_overlaps(&res, &res1)) { > + dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", > + mm_name[0], mm_name[1]); > + dev_err(dev, "%pR overlaps %pR\n", &res1, &res); > + > + return -EFAULT; > + } > + } > + } > + > + syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr"); > + if (IS_ERR(syscfg_regmap)) { > + dev_err(dev, "Failed to get st,syscfg-amcr property\n"); > + return PTR_ERR(syscfg_regmap); Same comments as usual, see further. > + } > + > + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1, > + &amcr_base); > + if (ret) > + return ret; > + > + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2, > + &amcr_mask); > + if (ret) > + return ret; > + > + amcr = mm_ospi2_size / SZ_64M; > + > + if (set) > + regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr); > + > + /* read AMCR and check coherency with memory-map areas defined in DT */ > + regmap_read(syscfg_regmap, amcr_base, &read_amcr); > + read_amcr = read_amcr >> (ffs(amcr_mask) - 1); > + > + if (amcr != read_amcr) { > + dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); > + ret = -EINVAL; > + } > + > + return ret; > +} > + > +static int stm32_omm_enable_child_clock(struct device *dev, bool enable) > +{ > + /* As there is only 2 children, remember first child in case of error */ > + struct clk *first_child_clk = NULL; > + struct stm32_omm *omm = dev_get_drvdata(dev); > + u8 i; > + int ret; > + > + for (i = 0; i < omm->nb_child; i++) { > + if (enable) { > + ret = clk_prepare_enable(omm->child[i].clk); > + if (ret) { > + if (first_child_clk) > + clk_disable_unprepare(first_child_clk); Function is called stm32_omm_enable_child_clock() but you disable. Confusing. Probably should be called toggle. > + > + dev_err(dev, "Can not enable clock\n"); > + return ret; > + } > + } else { > + clk_disable_unprepare(omm->child[i].clk); > + } > + > + first_child_clk = omm->child[i].clk; > + } > + > + return 0; > +} > + > +static int stm32_omm_configure(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + struct reset_control *rstc; > + unsigned long clk_rate, clk_rate_max = 0; > + int ret; > + u8 i; > + u32 mux = 0; That's one big mess. Do not mix initialized declarations with non-initialized in the same line. Then group initialized ones together and use some reverse christmas tree. Then the rest also should be organized. > + u32 cssel_ovr = 0; > + u32 req2ack = 0; > + > + omm->clk = devm_clk_get(dev, NULL); So here devm_clk_get, but later of_clk_get... > + if (IS_ERR(omm->clk)) { > + dev_err(dev, "Failed to get OMM clock (%ld)\n", > + PTR_ERR(omm->clk)); > + No. There is no such code anywhere. Please don't upstream downstream, but take upstream as template. It is *always* return dev_err_probe. You are flooding dmesg in deferral for no reason. > + return PTR_ERR(omm->clk); > + } > + > + ret = pm_runtime_resume_and_get(dev); > + if (ret < 0) > + return ret; > + > + /* parse children's clock */ > + for (i = 0; i < omm->nb_child; i++) { > + clk_rate = clk_get_rate(omm->child[i].clk); > + if (!clk_rate) { > + dev_err(dev, "Invalid clock rate\n"); > + pm_runtime_disable(dev); > + goto err_clk_disable; > + } > + > + if (clk_rate > clk_rate_max) > + clk_rate_max = clk_rate; > + } > + > + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); > + if (IS_ERR(rstc)) { > + ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); > + pm_runtime_disable(dev); Why? It was not enabled in this function. I cannot follow the logic, feels like random set of calls. Each of your function is supposed to reverse ONLY what it done so far. > + goto err_clk_disable; > + } > + > + reset_control_assert(rstc); > + udelay(2); > + reset_control_deassert(rstc); > + > + omm->cr = readl_relaxed(omm->io_base + OMM_CR); > + /* optional */ > + ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux); > + if (!ret) { > + if (mux & CR_MUXEN) { > + ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", > + &req2ack); > + if (!ret && !req2ack) { > + req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; > + > + if (req2ack > 256) > + req2ack = 256; > + } > + > + req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); > + > + omm->cr &= ~CR_REQ2ACK_MASK; > + omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack); > + > + /* > + * If the mux is enabled, the 2 OSPI clocks have to be > + * always enabled > + */ > + ret = stm32_omm_enable_child_clock(dev, true); > + if (ret) { > + pm_runtime_disable(dev); > + goto err_clk_disable; > + } > + } > + > + omm->cr &= ~CR_MUXENMODE_MASK; > + omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux); > + } > + > + /* optional */ > + ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr); > + if (!ret) { > + omm->cr &= ~CR_CSSEL_OVR_MASK; > + omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); > + omm->cr |= CR_CSSEL_OVR_EN; > + } > + > + omm->restore_omm = true; > + writel_relaxed(omm->cr, omm->io_base + OMM_CR); > + > + ret = stm32_omm_set_amcr(dev, true); > + > +err_clk_disable: > + pm_runtime_put_sync_suspend(dev); > + > + return ret; > +} > + > +static int stm32_omm_check_access(struct device *dev, struct device_node *np) > +{ > + struct stm32_firewall firewall; > + int ret; > + > + ret = stm32_firewall_get_firewall(np, &firewall, 1); > + if (ret) > + return ret; > + > + return stm32_firewall_grant_access(&firewall); > +} > + > +static int stm32_omm_disable_child(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + struct reset_control *reset; > + int ret; > + u8 i; > + > + for (i = 0; i < omm->nb_child; i++) { > + ret = clk_prepare_enable(omm->child[i].clk); > + if (ret) { > + dev_err(dev, "Can not enable clock\n"); > + return ret; > + } > + > + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); > + if (IS_ERR(reset)) { > + dev_err(dev, "Can't get child reset\n"); Why do you get reset of child? Parent is not suppposed to poke there. You might not have the reset there in the first place and it would not be an error. > + return PTR_ERR(reset); > + }; > + > + /* reset OSPI to ensure CR_EN bit is set to 0 */ > + reset_control_assert(reset); > + udelay(2); > + reset_control_deassert(reset); No, the child should handle this, not parent. > + > + reset_control_put(reset); > + clk_disable_unprepare(omm->child[i].clk); > + } > + > + return 0; > +} > + > +static int stm32_omm_probe(struct platform_device *pdev) > +{ > + struct platform_device *vdev; > + struct device *dev = &pdev->dev; > + struct stm32_omm *omm; > + struct clk *clk; > + int ret; > + u8 child_access_granted = 0; Keep inits/assignments together > + u8 i, j; > + bool child_access[OMM_CHILD_NB]; > + > + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); > + if (!omm) > + return -ENOMEM; > + > + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); > + if (IS_ERR(omm->io_base)) > + return PTR_ERR(omm->io_base); > + > + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); > + if (IS_ERR(omm->mm_res)) > + return PTR_ERR(omm->mm_res); > + > + /* check child's access */ > + for_each_child_of_node_scoped(dev->of_node, child) { > + if (omm->nb_child >= OMM_CHILD_NB) { > + dev_err(dev, "Bad DT, found too much children\n"); > + ret = -E2BIG; > + goto err_clk_release; > + } > + > + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { > + ret = -EINVAL; > + goto err_clk_release; > + } > + > + ret = stm32_omm_check_access(dev, child); > + if (ret < 0 && ret != -EACCES) > + goto err_clk_release; > + > + child_access[omm->nb_child] = false; > + if (!ret) { > + child_access_granted++; > + child_access[omm->nb_child] = true; > + } > + > + omm->child[omm->nb_child].node = child; > + > + clk = of_clk_get(child, 0); Why are you taking children clock? And why with this API, not clk_get? This looks like mixing clock provider in the clock consumer. > + if (IS_ERR(clk)) { > + dev_err(dev, "Can't get child clock\n"); Syntax is always return dev_err_probe (or ret = dev_err_probe). > + ret = PTR_ERR(clk); > + goto err_clk_release; > + }; > + > + omm->child[omm->nb_child].clk = clk; > + omm->nb_child++; > + } > + > + if (omm->nb_child != OMM_CHILD_NB) { > + ret = -EINVAL; > + goto err_clk_release; > + } > + > + platform_set_drvdata(pdev, omm); > + > + pm_runtime_enable(dev); > + > + /* check if OMM's resource access is granted */ > + ret = stm32_omm_check_access(dev, dev->of_node); > + if (ret < 0 && ret != -EACCES) > + goto err_clk_release; > + > + if (!ret && child_access_granted == OMM_CHILD_NB) { > + /* Ensure both OSPI instance are disabled before configuring OMM */ > + ret = stm32_omm_disable_child(dev); > + if (ret) > + goto err_clk_release; > + > + ret = stm32_omm_configure(dev); > + if (ret) > + goto err_clk_release; > + } else { > + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); > + /* > + * AMCR can't be set, so check if current value is coherent > + * with memory-map areas defined in DT > + */ > + ret = stm32_omm_set_amcr(dev, false); > + if (ret) > + goto err_clk_release; > + } > + > + /* for each child, if resource access is granted and status "okay", probe it */ > + for (i = 0; i < omm->nb_child; i++) { > + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) If you have a device available, why do you create one more platform device? > + continue; > + > + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); Why you cannot just populate the children? > + if (!vdev) { > + dev_err(dev, "Failed to create Octo Memory Manager child\n"); > + for (j = i; j > 0; --j) { > + if (omm->child[j].dev) > + of_platform_device_destroy(omm->child[j].dev, NULL); > + } > + > + ret = -EINVAL; > + goto err_clk_release; > + } > + omm->child[i].dev = &vdev->dev; > + } > + > +err_clk_release: > + for (i = 0; i < omm->nb_child; i++) > + clk_put(omm->child[i].clk); > + > + return ret; > +} > + > +static void stm32_omm_remove(struct platform_device *pdev) > +{ > + struct stm32_omm *omm = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < omm->nb_child; i++) > + if (omm->child[i].dev) > + of_platform_device_destroy(omm->child[i].dev, NULL); > + > + if (omm->cr & CR_MUXEN) > + stm32_omm_enable_child_clock(&pdev->dev, false); > + > + pm_runtime_disable(&pdev->dev); > +} > + > +static const struct of_device_id stm32_omm_of_match[] = { > + { .compatible = "st,stm32mp25-omm", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, stm32_omm_of_match); > + > +static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + > + clk_disable_unprepare(omm->clk); > + > + return 0; > +} > + > +static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + > + return clk_prepare_enable(omm->clk); > +} > + > +static int __maybe_unused stm32_omm_suspend(struct device *dev) > +{ > + struct stm32_omm *omm = dev_get_drvdata(dev); > + > + if (omm->restore_omm && omm->cr & CR_MUXEN) > + stm32_omm_enable_child_clock(dev, false); Why do you enable child clock for suspend? > + > + return pinctrl_pm_select_sleep_state(dev); > +} > + Best regards, Krzysztof
On 3/11/25 17:04, Krzysztof Kozlowski wrote: > On 19/02/2025 09:00, patrice.chotard@foss.st.com wrote: >> From: Patrice Chotard <patrice.chotard@foss.st.com> >> >> Octo Memory Manager driver (OMM) manages: >> - the muxing between 2 OSPI busses and 2 output ports. >> There are 4 possible muxing configurations: >> - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 >> output is on port 2 >> - OSPI1 and OSPI2 are multiplexed over the same output port 1 >> - swapped mode (no multiplexing), OSPI1 output is on port 2, >> OSPI2 output is on port 1 >> - OSPI1 and OSPI2 are multiplexed over the same output port 2 >> - the split of the memory area shared between the 2 OSPI instances. >> - chip select selection override. >> - the time between 2 transactions in multiplexed mode. >> - check firewall access. >> >> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> >> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> > > Incorrect chain. You sent it, so you must be the last person signing it. ok > > I was waiting for any ST review... did not happen, so if you wonder how > to speed things up, you got a hint. Anyway, many questions futher. > > >> + >> + if (i == 1) { >> + mm_ospi2_size = resource_size(&res); >> + >> + /* check that OMM memory region 1 doesn't overlap memory region 2 */ >> + if (resource_overlaps(&res, &res1)) { >> + dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", >> + mm_name[0], mm_name[1]); >> + dev_err(dev, "%pR overlaps %pR\n", &res1, &res); >> + >> + return -EFAULT; >> + } >> + } >> + } >> + >> + syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr"); >> + if (IS_ERR(syscfg_regmap)) { >> + dev_err(dev, "Failed to get st,syscfg-amcr property\n"); >> + return PTR_ERR(syscfg_regmap); > > Same comments as usual, see further. ok, will use dev_err_probe() > >> + } >> + >> + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1, >> + &amcr_base); >> + if (ret) >> + return ret; >> + >> + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2, >> + &amcr_mask); >> + if (ret) >> + return ret; >> + >> + amcr = mm_ospi2_size / SZ_64M; >> + >> + if (set) >> + regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr); >> + >> + /* read AMCR and check coherency with memory-map areas defined in DT */ >> + regmap_read(syscfg_regmap, amcr_base, &read_amcr); >> + read_amcr = read_amcr >> (ffs(amcr_mask) - 1); >> + >> + if (amcr != read_amcr) { >> + dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); >> + ret = -EINVAL; >> + } >> + >> + return ret; >> +} >> + >> +static int stm32_omm_enable_child_clock(struct device *dev, bool enable) >> +{ >> + /* As there is only 2 children, remember first child in case of error */ >> + struct clk *first_child_clk = NULL; >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + u8 i; >> + int ret; >> + >> + for (i = 0; i < omm->nb_child; i++) { >> + if (enable) { >> + ret = clk_prepare_enable(omm->child[i].clk); >> + if (ret) { >> + if (first_child_clk) >> + clk_disable_unprepare(first_child_clk); > > Function is called stm32_omm_enable_child_clock() but you disable. > Confusing. Probably should be called toggle. Agree, i will rename it to stm32_omm_toggle_child_clock > >> + >> + dev_err(dev, "Can not enable clock\n"); >> + return ret; >> + } >> + } else { >> + clk_disable_unprepare(omm->child[i].clk); >> + } >> + >> + first_child_clk = omm->child[i].clk; >> + } >> + >> + return 0; >> +} >> + >> +static int stm32_omm_configure(struct device *dev) >> +{ >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + struct reset_control *rstc; >> + unsigned long clk_rate, clk_rate_max = 0; >> + int ret; >> + u8 i; >> + u32 mux = 0; > > That's one big mess. Do not mix initialized declarations with > non-initialized in the same line. Then group initialized ones together > and use some reverse christmas tree. > > Then the rest also should be organized. ok > >> + u32 cssel_ovr = 0; >> + u32 req2ack = 0; >> + >> + omm->clk = devm_clk_get(dev, NULL); > > So here devm_clk_get, but later of_clk_get... > >> + if (IS_ERR(omm->clk)) { >> + dev_err(dev, "Failed to get OMM clock (%ld)\n", >> + PTR_ERR(omm->clk)); >> + > > No. There is no such code anywhere. Please don't upstream downstream, > but take upstream as template. > > It is *always* return dev_err_probe. You are flooding dmesg in deferral > for no reason. ok, will use dev_err_probe() > >> + return PTR_ERR(omm->clk); >> + } >> + >> + ret = pm_runtime_resume_and_get(dev); >> + if (ret < 0) >> + return ret; >> + >> + /* parse children's clock */ >> + for (i = 0; i < omm->nb_child; i++) { >> + clk_rate = clk_get_rate(omm->child[i].clk); >> + if (!clk_rate) { >> + dev_err(dev, "Invalid clock rate\n"); >> + pm_runtime_disable(dev); >> + goto err_clk_disable; >> + } >> + >> + if (clk_rate > clk_rate_max) >> + clk_rate_max = clk_rate; >> + } >> + >> + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); >> + if (IS_ERR(rstc)) { >> + ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); >> + pm_runtime_disable(dev); > > Why? It was not enabled in this function. I cannot follow the logic, > feels like random set of calls. Each of your function is supposed to > reverse ONLY what it done so far. right, i will move pm_runtime_disable() outside stm32_omm_enable_child_clock() > >> + goto err_clk_disable; >> + } >> + >> + reset_control_assert(rstc); >> + udelay(2); >> + reset_control_deassert(rstc); >> + >> + omm->cr = readl_relaxed(omm->io_base + OMM_CR); >> + /* optional */ >> + ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux); >> + if (!ret) { >> + if (mux & CR_MUXEN) { >> + ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", >> + &req2ack); >> + if (!ret && !req2ack) { >> + req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; >> + >> + if (req2ack > 256) >> + req2ack = 256; >> + } >> + >> + req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); >> + >> + omm->cr &= ~CR_REQ2ACK_MASK; >> + omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack); >> + >> + /* >> + * If the mux is enabled, the 2 OSPI clocks have to be >> + * always enabled >> + */ >> + ret = stm32_omm_enable_child_clock(dev, true); >> + if (ret) { >> + pm_runtime_disable(dev); >> + goto err_clk_disable; >> + } >> + } >> + >> + omm->cr &= ~CR_MUXENMODE_MASK; >> + omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux); >> + } >> + >> + /* optional */ >> + ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr); >> + if (!ret) { >> + omm->cr &= ~CR_CSSEL_OVR_MASK; >> + omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); >> + omm->cr |= CR_CSSEL_OVR_EN; >> + } >> + >> + omm->restore_omm = true; >> + writel_relaxed(omm->cr, omm->io_base + OMM_CR); >> + >> + ret = stm32_omm_set_amcr(dev, true); >> + >> +err_clk_disable: >> + pm_runtime_put_sync_suspend(dev); >> + >> + return ret; >> +} >> + >> +static int stm32_omm_check_access(struct device *dev, struct device_node *np) >> +{ >> + struct stm32_firewall firewall; >> + int ret; >> + >> + ret = stm32_firewall_get_firewall(np, &firewall, 1); >> + if (ret) >> + return ret; >> + >> + return stm32_firewall_grant_access(&firewall); >> +} >> + >> +static int stm32_omm_disable_child(struct device *dev) >> +{ >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + struct reset_control *reset; >> + int ret; >> + u8 i; >> + >> + for (i = 0; i < omm->nb_child; i++) { >> + ret = clk_prepare_enable(omm->child[i].clk); >> + if (ret) { >> + dev_err(dev, "Can not enable clock\n"); >> + return ret; >> + } >> + >> + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); >> + if (IS_ERR(reset)) { >> + dev_err(dev, "Can't get child reset\n"); > > Why do you get reset of child? Parent is not suppposed to poke there. > You might not have the reset there in the first place and it would not > be an error. By ressetting child (OSPI), we ensure they are disabled and in a known state. See the comment below. > > >> + return PTR_ERR(reset); >> + }; >> + >> + /* reset OSPI to ensure CR_EN bit is set to 0 */ >> + reset_control_assert(reset); >> + udelay(2); >> + reset_control_deassert(reset); > > No, the child should handle this, not parent. Octo Memory Manager can only be configured if both child are disabled. That's why here, parent handles this. > >> + >> + reset_control_put(reset); >> + clk_disable_unprepare(omm->child[i].clk); >> + } >> + >> + return 0; >> +} >> + >> +static int stm32_omm_probe(struct platform_device *pdev) >> +{ >> + struct platform_device *vdev; >> + struct device *dev = &pdev->dev; >> + struct stm32_omm *omm; >> + struct clk *clk; >> + int ret; >> + u8 child_access_granted = 0; > > Keep inits/assignments together ok > >> + u8 i, j; >> + bool child_access[OMM_CHILD_NB]; >> + >> + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); >> + if (!omm) >> + return -ENOMEM; >> + >> + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); >> + if (IS_ERR(omm->io_base)) >> + return PTR_ERR(omm->io_base); >> + >> + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); >> + if (IS_ERR(omm->mm_res)) >> + return PTR_ERR(omm->mm_res); >> + >> + /* check child's access */ >> + for_each_child_of_node_scoped(dev->of_node, child) { >> + if (omm->nb_child >= OMM_CHILD_NB) { >> + dev_err(dev, "Bad DT, found too much children\n"); >> + ret = -E2BIG; >> + goto err_clk_release; >> + } >> + >> + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { >> + ret = -EINVAL; >> + goto err_clk_release; >> + } >> + >> + ret = stm32_omm_check_access(dev, child); >> + if (ret < 0 && ret != -EACCES) >> + goto err_clk_release; >> + >> + child_access[omm->nb_child] = false; >> + if (!ret) { >> + child_access_granted++; >> + child_access[omm->nb_child] = true; >> + } >> + >> + omm->child[omm->nb_child].node = child; >> + >> + clk = of_clk_get(child, 0); > > Why are you taking children clock? And why with this API, not clk_get? I need children's clock to reset them. Why of_clk_get() usage is a problem here ? i can't get your point ? > This looks like mixing clock provider in the clock consumer. > >> + if (IS_ERR(clk)) { >> + dev_err(dev, "Can't get child clock\n"); > > Syntax is always return dev_err_probe (or ret = dev_err_probe). ok > >> + ret = PTR_ERR(clk); >> + goto err_clk_release; >> + }; >> + >> + omm->child[omm->nb_child].clk = clk; >> + omm->nb_child++; >> + } >> + >> + if (omm->nb_child != OMM_CHILD_NB) { >> + ret = -EINVAL; >> + goto err_clk_release; >> + } >> + >> + platform_set_drvdata(pdev, omm); >> + >> + pm_runtime_enable(dev); >> + >> + /* check if OMM's resource access is granted */ >> + ret = stm32_omm_check_access(dev, dev->of_node); >> + if (ret < 0 && ret != -EACCES) >> + goto err_clk_release; >> + >> + if (!ret && child_access_granted == OMM_CHILD_NB) { >> + /* Ensure both OSPI instance are disabled before configuring OMM */ >> + ret = stm32_omm_disable_child(dev); >> + if (ret) >> + goto err_clk_release; >> + >> + ret = stm32_omm_configure(dev); >> + if (ret) >> + goto err_clk_release; >> + } else { >> + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); >> + /* >> + * AMCR can't be set, so check if current value is coherent >> + * with memory-map areas defined in DT >> + */ >> + ret = stm32_omm_set_amcr(dev, false); >> + if (ret) >> + goto err_clk_release; >> + } >> + >> + /* for each child, if resource access is granted and status "okay", probe it */ >> + for (i = 0; i < omm->nb_child; i++) { >> + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) > > If you have a device available, why do you create one more platform device? > >> + continue; >> + >> + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); > > Why you cannot just populate the children? I can't use of_platform_populate(), by default it will populate all OMM's child. Whereas here, we want to probe only the OMM's child which match our criteria. > >> + if (!vdev) { >> + dev_err(dev, "Failed to create Octo Memory Manager child\n"); >> + for (j = i; j > 0; --j) { >> + if (omm->child[j].dev) >> + of_platform_device_destroy(omm->child[j].dev, NULL); >> + } >> + >> + ret = -EINVAL; >> + goto err_clk_release; >> + } >> + omm->child[i].dev = &vdev->dev; >> + } >> + >> +err_clk_release: >> + for (i = 0; i < omm->nb_child; i++) >> + clk_put(omm->child[i].clk); >> + >> + return ret; >> +} >> + >> +static void stm32_omm_remove(struct platform_device *pdev) >> +{ >> + struct stm32_omm *omm = platform_get_drvdata(pdev); >> + int i; >> + >> + for (i = 0; i < omm->nb_child; i++) >> + if (omm->child[i].dev) >> + of_platform_device_destroy(omm->child[i].dev, NULL); >> + >> + if (omm->cr & CR_MUXEN) >> + stm32_omm_enable_child_clock(&pdev->dev, false); >> + >> + pm_runtime_disable(&pdev->dev); >> +} >> + >> +static const struct of_device_id stm32_omm_of_match[] = { >> + { .compatible = "st,stm32mp25-omm", }, >> + {} >> +}; >> +MODULE_DEVICE_TABLE(of, stm32_omm_of_match); >> + >> +static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) >> +{ >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + >> + clk_disable_unprepare(omm->clk); >> + >> + return 0; >> +} >> + >> +static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) >> +{ >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + >> + return clk_prepare_enable(omm->clk); >> +} >> + >> +static int __maybe_unused stm32_omm_suspend(struct device *dev) >> +{ >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + >> + if (omm->restore_omm && omm->cr & CR_MUXEN) >> + stm32_omm_enable_child_clock(dev, false); > > Why do you enable child clock for suspend? The child clock is disbaled here, but as you indicated earlier in this patch, stm32_omm_enable_child_clock() will be renamed stm32_omm_toggle_child_clock() to avoid confussion. Thanks Patrice > >> + >> + return pinctrl_pm_select_sleep_state(dev); >> +} >> + > > > Best regards, > Krzysztof
On 10/03/2025 14:52, Patrice CHOTARD wrote: >> +module_platform_driver(stm32_omm_driver); >> + >> +MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver"); >> +MODULE_LICENSE("GPL"); > > > Hi all, > > Anybody alse has additionnal remarks on this driver ? BTW, you explained nothing about merging in the cover letter, mark already took the patch, but I see there is dependency. This cannot be merged and pinging will not change anything here. In the future, ALWAYS document dependencies between patches and make it explicit for the maintainers. Best regards, Krzysztof
On 12/03/2025 15:23, Patrice CHOTARD wrote: >>> +static int stm32_omm_disable_child(struct device *dev) >>> +{ >>> + struct stm32_omm *omm = dev_get_drvdata(dev); >>> + struct reset_control *reset; >>> + int ret; >>> + u8 i; >>> + >>> + for (i = 0; i < omm->nb_child; i++) { >>> + ret = clk_prepare_enable(omm->child[i].clk); >>> + if (ret) { >>> + dev_err(dev, "Can not enable clock\n"); >>> + return ret; >>> + } >>> + >>> + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); >>> + if (IS_ERR(reset)) { >>> + dev_err(dev, "Can't get child reset\n"); >> >> Why do you get reset of child? Parent is not suppposed to poke there. >> You might not have the reset there in the first place and it would not >> be an error. > > By ressetting child (OSPI), we ensure they are disabled and in a known state. > See the comment below. > >> >> >>> + return PTR_ERR(reset); >>> + }; >>> + >>> + /* reset OSPI to ensure CR_EN bit is set to 0 */ >>> + reset_control_assert(reset); >>> + udelay(2); >>> + reset_control_deassert(reset); >> >> No, the child should handle this, not parent. > > Octo Memory Manager can only be configured if both child are disabled. > That's why here, parent handles this. So if device by any chance started and is doing some useful work, then you cancel that work and reset it? And what if child does not have reset line? Your binding allows that, so how is it supposed to work then? This also leads me to questions about bindings - if you need to assert some reset, doesn't it mean that these resets are also coming through this device so they are part of this device node? > >> >>> + >>> + reset_control_put(reset); >>> + clk_disable_unprepare(omm->child[i].clk); >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static int stm32_omm_probe(struct platform_device *pdev) >>> +{ >>> + struct platform_device *vdev; >>> + struct device *dev = &pdev->dev; >>> + struct stm32_omm *omm; >>> + struct clk *clk; >>> + int ret; >>> + u8 child_access_granted = 0; >> >> Keep inits/assignments together > > ok > >> >>> + u8 i, j; >>> + bool child_access[OMM_CHILD_NB]; >>> + >>> + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); >>> + if (!omm) >>> + return -ENOMEM; >>> + >>> + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); >>> + if (IS_ERR(omm->io_base)) >>> + return PTR_ERR(omm->io_base); >>> + >>> + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); >>> + if (IS_ERR(omm->mm_res)) >>> + return PTR_ERR(omm->mm_res); >>> + >>> + /* check child's access */ >>> + for_each_child_of_node_scoped(dev->of_node, child) { >>> + if (omm->nb_child >= OMM_CHILD_NB) { >>> + dev_err(dev, "Bad DT, found too much children\n"); >>> + ret = -E2BIG; >>> + goto err_clk_release; >>> + } >>> + >>> + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { >>> + ret = -EINVAL; >>> + goto err_clk_release; >>> + } >>> + >>> + ret = stm32_omm_check_access(dev, child); >>> + if (ret < 0 && ret != -EACCES) >>> + goto err_clk_release; >>> + >>> + child_access[omm->nb_child] = false; >>> + if (!ret) { >>> + child_access_granted++; >>> + child_access[omm->nb_child] = true; >>> + } >>> + >>> + omm->child[omm->nb_child].node = child; >>> + >>> + clk = of_clk_get(child, 0); >> >> Why are you taking children clock? And why with this API, not clk_get? > > I need children's clock to reset them. The device driver should reset its device. It is not a discoverable bus, that would explain power sequencing from the parent. > Why of_clk_get() usage is a problem here ? i can't get your point ? Because it is not the API which device drivers should use. You should use clk_get or devm_clk_get. > >> This looks like mixing clock provider in the clock consumer. >> >>> + if (IS_ERR(clk)) { >>> + dev_err(dev, "Can't get child clock\n"); >> >> Syntax is always return dev_err_probe (or ret = dev_err_probe). > > ok > >> >>> + ret = PTR_ERR(clk); >>> + goto err_clk_release; >>> + }; >>> + >>> + omm->child[omm->nb_child].clk = clk; >>> + omm->nb_child++; >>> + } >>> + >>> + if (omm->nb_child != OMM_CHILD_NB) { >>> + ret = -EINVAL; >>> + goto err_clk_release; >>> + } >>> + >>> + platform_set_drvdata(pdev, omm); >>> + >>> + pm_runtime_enable(dev); >>> + >>> + /* check if OMM's resource access is granted */ >>> + ret = stm32_omm_check_access(dev, dev->of_node); >>> + if (ret < 0 && ret != -EACCES) >>> + goto err_clk_release; >>> + >>> + if (!ret && child_access_granted == OMM_CHILD_NB) { >>> + /* Ensure both OSPI instance are disabled before configuring OMM */ >>> + ret = stm32_omm_disable_child(dev); >>> + if (ret) >>> + goto err_clk_release; >>> + >>> + ret = stm32_omm_configure(dev); >>> + if (ret) >>> + goto err_clk_release; >>> + } else { >>> + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); >>> + /* >>> + * AMCR can't be set, so check if current value is coherent >>> + * with memory-map areas defined in DT >>> + */ >>> + ret = stm32_omm_set_amcr(dev, false); >>> + if (ret) >>> + goto err_clk_release; >>> + } >>> + >>> + /* for each child, if resource access is granted and status "okay", probe it */ >>> + for (i = 0; i < omm->nb_child; i++) { >>> + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) >> >> If you have a device available, why do you create one more platform device? >> >>> + continue; >>> + >>> + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); >> >> Why you cannot just populate the children? > > I can't use of_platform_populate(), by default it will populate all OMM's child. > Whereas here, we want to probe only the OMM's child which match our criteria. Why wouldn't you populate everyone? The task of bus driver is not to filter out DT. If you got such DT - with all device nodes - you are expected to populate all of them. Otherwise, if you do not want all of them, it is expected that firmware or bootloader will give you DT without these nodes. Best regards, Krzysztof
On 3/13/25 08:33, Krzysztof Kozlowski wrote: > On 12/03/2025 15:23, Patrice CHOTARD wrote: >>>> +static int stm32_omm_disable_child(struct device *dev) >>>> +{ >>>> + struct stm32_omm *omm = dev_get_drvdata(dev); >>>> + struct reset_control *reset; >>>> + int ret; >>>> + u8 i; >>>> + >>>> + for (i = 0; i < omm->nb_child; i++) { >>>> + ret = clk_prepare_enable(omm->child[i].clk); >>>> + if (ret) { >>>> + dev_err(dev, "Can not enable clock\n"); >>>> + return ret; >>>> + } >>>> + >>>> + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); >>>> + if (IS_ERR(reset)) { >>>> + dev_err(dev, "Can't get child reset\n"); >>> >>> Why do you get reset of child? Parent is not suppposed to poke there. >>> You might not have the reset there in the first place and it would not >>> be an error. >> >> By ressetting child (OSPI), we ensure they are disabled and in a known state. >> See the comment below. >> >>> >>> >>>> + return PTR_ERR(reset); >>>> + }; >>>> + >>>> + /* reset OSPI to ensure CR_EN bit is set to 0 */ >>>> + reset_control_assert(reset); >>>> + udelay(2); >>>> + reset_control_deassert(reset); >>> >>> No, the child should handle this, not parent. >> >> Octo Memory Manager can only be configured if both child are disabled. >> That's why here, parent handles this. > > So if device by any chance started and is doing some useful work, then > you cancel that work and reset it? stm32_omm_configure() is only called if we get access granted on both children. That means we are authorized to use these devices, so we can reset them. > > And what if child does not have reset line? Your binding allows that, so > how is it supposed to work then? Ah yes, you are right, the OSPI bindings need to be updated by requiring reset lines and the driver spi-stm32-ospi.c as well. I will send a fix for that. Thanks for pointing this. > > This also leads me to questions about bindings - if you need to assert > some reset, doesn't it mean that these resets are also coming through > this device so they are part of this device node? As we are able to retrieve children's reset from their respective node, if you don't mind, OMM bindings can be kept as it's currently. And another information, on some MP2 SoCs family, there is only one OSPI instance. So for these SoCs, there is no Octo Memory Manager. > >> >>> >>>> + >>>> + reset_control_put(reset); >>>> + clk_disable_unprepare(omm->child[i].clk); >>>> + } >>>> + >>>> + return 0; >>>> +} >>>> + >>>> +static int stm32_omm_probe(struct platform_device *pdev) >>>> +{ >>>> + struct platform_device *vdev; >>>> + struct device *dev = &pdev->dev; >>>> + struct stm32_omm *omm; >>>> + struct clk *clk; >>>> + int ret; >>>> + u8 child_access_granted = 0; >>> >>> Keep inits/assignments together >> >> ok >> >>> >>>> + u8 i, j; >>>> + bool child_access[OMM_CHILD_NB]; >>>> + >>>> + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); >>>> + if (!omm) >>>> + return -ENOMEM; >>>> + >>>> + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); >>>> + if (IS_ERR(omm->io_base)) >>>> + return PTR_ERR(omm->io_base); >>>> + >>>> + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); >>>> + if (IS_ERR(omm->mm_res)) >>>> + return PTR_ERR(omm->mm_res); >>>> + >>>> + /* check child's access */ >>>> + for_each_child_of_node_scoped(dev->of_node, child) { >>>> + if (omm->nb_child >= OMM_CHILD_NB) { >>>> + dev_err(dev, "Bad DT, found too much children\n"); >>>> + ret = -E2BIG; >>>> + goto err_clk_release; >>>> + } >>>> + >>>> + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { >>>> + ret = -EINVAL; >>>> + goto err_clk_release; >>>> + } >>>> + >>>> + ret = stm32_omm_check_access(dev, child); >>>> + if (ret < 0 && ret != -EACCES) >>>> + goto err_clk_release; >>>> + >>>> + child_access[omm->nb_child] = false; >>>> + if (!ret) { >>>> + child_access_granted++; >>>> + child_access[omm->nb_child] = true; >>>> + } >>>> + >>>> + omm->child[omm->nb_child].node = child; >>>> + >>>> + clk = of_clk_get(child, 0); >>> >>> Why are you taking children clock? And why with this API, not clk_get? >> >> I need children's clock to reset them. > > > The device driver should reset its device. It is not a discoverable bus, > that would explain power sequencing from the parent. > >> Why of_clk_get() usage is a problem here ? i can't get your point ? > > Because it is not the API which device drivers should use. You should > use clk_get or devm_clk_get. ok, i will update this part using clk_get(). > > >> >>> This looks like mixing clock provider in the clock consumer. >>> >>>> + if (IS_ERR(clk)) { >>>> + dev_err(dev, "Can't get child clock\n"); >>> >>> Syntax is always return dev_err_probe (or ret = dev_err_probe). >> >> ok >> >>> >>>> + ret = PTR_ERR(clk); >>>> + goto err_clk_release; >>>> + }; >>>> + >>>> + omm->child[omm->nb_child].clk = clk; >>>> + omm->nb_child++; >>>> + } >>>> + >>>> + if (omm->nb_child != OMM_CHILD_NB) { >>>> + ret = -EINVAL; >>>> + goto err_clk_release; >>>> + } >>>> + >>>> + platform_set_drvdata(pdev, omm); >>>> + >>>> + pm_runtime_enable(dev); >>>> + >>>> + /* check if OMM's resource access is granted */ >>>> + ret = stm32_omm_check_access(dev, dev->of_node); >>>> + if (ret < 0 && ret != -EACCES) >>>> + goto err_clk_release; >>>> + >>>> + if (!ret && child_access_granted == OMM_CHILD_NB) { >>>> + /* Ensure both OSPI instance are disabled before configuring OMM */ >>>> + ret = stm32_omm_disable_child(dev); >>>> + if (ret) >>>> + goto err_clk_release; >>>> + >>>> + ret = stm32_omm_configure(dev); >>>> + if (ret) >>>> + goto err_clk_release; >>>> + } else { >>>> + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); >>>> + /* >>>> + * AMCR can't be set, so check if current value is coherent >>>> + * with memory-map areas defined in DT >>>> + */ >>>> + ret = stm32_omm_set_amcr(dev, false); >>>> + if (ret) >>>> + goto err_clk_release; >>>> + } >>>> + >>>> + /* for each child, if resource access is granted and status "okay", probe it */ >>>> + for (i = 0; i < omm->nb_child; i++) { >>>> + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) >>> >>> If you have a device available, why do you create one more platform device? >>> >>>> + continue; >>>> + >>>> + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); >>> >>> Why you cannot just populate the children? >> >> I can't use of_platform_populate(), by default it will populate all OMM's child. >> Whereas here, we want to probe only the OMM's child which match our criteria. > > > Why wouldn't you populate everyone? The task of bus driver is not to > filter out DT. If you got such DT - with all device nodes - you are > expected to populate all of them. Otherwise, if you do not want all of > them, it is expected that firmware or bootloader will give you DT > without these nodes. We don't want to populate every child by default because we can get cases where one child is shared between Cortex A and Cortex M. That's why we must check if access is granted which ensure that firewall semaphore is available (RIFSC semaphore in our case). Patrice > > Best regards, > Krzysztof
On 18/03/2025 14:40, Patrice CHOTARD wrote: > > > On 3/13/25 08:33, Krzysztof Kozlowski wrote: >> On 12/03/2025 15:23, Patrice CHOTARD wrote: >>>>> +static int stm32_omm_disable_child(struct device *dev) >>>>> +{ >>>>> + struct stm32_omm *omm = dev_get_drvdata(dev); >>>>> + struct reset_control *reset; >>>>> + int ret; >>>>> + u8 i; >>>>> + >>>>> + for (i = 0; i < omm->nb_child; i++) { >>>>> + ret = clk_prepare_enable(omm->child[i].clk); >>>>> + if (ret) { >>>>> + dev_err(dev, "Can not enable clock\n"); >>>>> + return ret; >>>>> + } >>>>> + >>>>> + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); >>>>> + if (IS_ERR(reset)) { >>>>> + dev_err(dev, "Can't get child reset\n"); >>>> >>>> Why do you get reset of child? Parent is not suppposed to poke there. >>>> You might not have the reset there in the first place and it would not >>>> be an error. >>> >>> By ressetting child (OSPI), we ensure they are disabled and in a known state. >>> See the comment below. >>> >>>> >>>> >>>>> + return PTR_ERR(reset); >>>>> + }; >>>>> + >>>>> + /* reset OSPI to ensure CR_EN bit is set to 0 */ >>>>> + reset_control_assert(reset); >>>>> + udelay(2); >>>>> + reset_control_deassert(reset); >>>> >>>> No, the child should handle this, not parent. >>> >>> Octo Memory Manager can only be configured if both child are disabled. >>> That's why here, parent handles this. >> >> So if device by any chance started and is doing some useful work, then >> you cancel that work and reset it? > > stm32_omm_configure() is only called if we get access granted on both children. > That means we are authorized to use these devices, so we can reset them. > >> >> And what if child does not have reset line? Your binding allows that, so >> how is it supposed to work then? > > Ah yes, you are right, the OSPI bindings need to be updated > by requiring reset lines and the driver spi-stm32-ospi.c as well. > I will send a fix for that. > > Thanks for pointing this. > >> >> This also leads me to questions about bindings - if you need to assert >> some reset, doesn't it mean that these resets are also coming through >> this device so they are part of this device node? > > As we are able to retrieve children's reset from their respective node, > if you don't mind, OMM bindings can be kept as it's currently. But that is what the entire discussion is about - I do mind. I said it already - you are not supposed to poke into child's node. If you need to toggle child's resources, then I claim these are your resources as well. > > And another information, on some MP2 SoCs family, there is only one > OSPI instance. So for these SoCs, there is no Octo Memory Manager. > >> >>> >>>> >>>>> + >>>>> + reset_control_put(reset); >>>>> + clk_disable_unprepare(omm->child[i].clk); >>>>> + } >>>>> + >>>>> + return 0; >>>>> +} >>>>> + >>>>> +static int stm32_omm_probe(struct platform_device *pdev) >>>>> +{ >>>>> + struct platform_device *vdev; >>>>> + struct device *dev = &pdev->dev; >>>>> + struct stm32_omm *omm; >>>>> + struct clk *clk; >>>>> + int ret; >>>>> + u8 child_access_granted = 0; >>>> >>>> Keep inits/assignments together >>> >>> ok >>> >>>> >>>>> + u8 i, j; >>>>> + bool child_access[OMM_CHILD_NB]; >>>>> + >>>>> + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); >>>>> + if (!omm) >>>>> + return -ENOMEM; >>>>> + >>>>> + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); >>>>> + if (IS_ERR(omm->io_base)) >>>>> + return PTR_ERR(omm->io_base); >>>>> + >>>>> + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); >>>>> + if (IS_ERR(omm->mm_res)) >>>>> + return PTR_ERR(omm->mm_res); >>>>> + >>>>> + /* check child's access */ >>>>> + for_each_child_of_node_scoped(dev->of_node, child) { >>>>> + if (omm->nb_child >= OMM_CHILD_NB) { >>>>> + dev_err(dev, "Bad DT, found too much children\n"); >>>>> + ret = -E2BIG; >>>>> + goto err_clk_release; >>>>> + } >>>>> + >>>>> + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { >>>>> + ret = -EINVAL; >>>>> + goto err_clk_release; >>>>> + } >>>>> + >>>>> + ret = stm32_omm_check_access(dev, child); >>>>> + if (ret < 0 && ret != -EACCES) >>>>> + goto err_clk_release; >>>>> + >>>>> + child_access[omm->nb_child] = false; >>>>> + if (!ret) { >>>>> + child_access_granted++; >>>>> + child_access[omm->nb_child] = true; >>>>> + } >>>>> + >>>>> + omm->child[omm->nb_child].node = child; >>>>> + >>>>> + clk = of_clk_get(child, 0); >>>> >>>> Why are you taking children clock? And why with this API, not clk_get? >>> >>> I need children's clock to reset them. >> >> >> The device driver should reset its device. It is not a discoverable bus, >> that would explain power sequencing from the parent. >> >>> Why of_clk_get() usage is a problem here ? i can't get your point ? >> >> Because it is not the API which device drivers should use. You should >> use clk_get or devm_clk_get. > > > ok, i will update this part using clk_get(). > >> >> >>> >>>> This looks like mixing clock provider in the clock consumer. >>>> >>>>> + if (IS_ERR(clk)) { >>>>> + dev_err(dev, "Can't get child clock\n"); >>>> >>>> Syntax is always return dev_err_probe (or ret = dev_err_probe). >>> >>> ok >>> >>>> >>>>> + ret = PTR_ERR(clk); >>>>> + goto err_clk_release; >>>>> + }; >>>>> + >>>>> + omm->child[omm->nb_child].clk = clk; >>>>> + omm->nb_child++; >>>>> + } >>>>> + >>>>> + if (omm->nb_child != OMM_CHILD_NB) { >>>>> + ret = -EINVAL; >>>>> + goto err_clk_release; >>>>> + } >>>>> + >>>>> + platform_set_drvdata(pdev, omm); >>>>> + >>>>> + pm_runtime_enable(dev); >>>>> + >>>>> + /* check if OMM's resource access is granted */ >>>>> + ret = stm32_omm_check_access(dev, dev->of_node); >>>>> + if (ret < 0 && ret != -EACCES) >>>>> + goto err_clk_release; >>>>> + >>>>> + if (!ret && child_access_granted == OMM_CHILD_NB) { >>>>> + /* Ensure both OSPI instance are disabled before configuring OMM */ >>>>> + ret = stm32_omm_disable_child(dev); >>>>> + if (ret) >>>>> + goto err_clk_release; >>>>> + >>>>> + ret = stm32_omm_configure(dev); >>>>> + if (ret) >>>>> + goto err_clk_release; >>>>> + } else { >>>>> + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); >>>>> + /* >>>>> + * AMCR can't be set, so check if current value is coherent >>>>> + * with memory-map areas defined in DT >>>>> + */ >>>>> + ret = stm32_omm_set_amcr(dev, false); >>>>> + if (ret) >>>>> + goto err_clk_release; >>>>> + } >>>>> + >>>>> + /* for each child, if resource access is granted and status "okay", probe it */ >>>>> + for (i = 0; i < omm->nb_child; i++) { >>>>> + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) >>>> >>>> If you have a device available, why do you create one more platform device? >>>> >>>>> + continue; >>>>> + >>>>> + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); >>>> >>>> Why you cannot just populate the children? >>> >>> I can't use of_platform_populate(), by default it will populate all OMM's child. >>> Whereas here, we want to probe only the OMM's child which match our criteria. >> >> >> Why wouldn't you populate everyone? The task of bus driver is not to >> filter out DT. If you got such DT - with all device nodes - you are >> expected to populate all of them. Otherwise, if you do not want all of >> them, it is expected that firmware or bootloader will give you DT >> without these nodes. > > We don't want to populate every child by default because we can get > cases where one child is shared between Cortex A and Cortex M. But in such case DTB would not have that child enabled. > That's why we must check if access is granted which ensure that > firewall semaphore is available (RIFSC semaphore in our case). If you do not have access, means child is assigned to other processor, right? In that case that child would not have been enabled in your DTB. Fix your DTB instead of creating another layer of handling children inside drivers. Best regards, Krzysztof
On 3/19/25 08:37, Krzysztof Kozlowski wrote: > On 18/03/2025 14:40, Patrice CHOTARD wrote: >> >> >> On 3/13/25 08:33, Krzysztof Kozlowski wrote: >>> On 12/03/2025 15:23, Patrice CHOTARD wrote: >>>>>> +static int stm32_omm_disable_child(struct device *dev) >>>>>> +{ >>>>>> + struct stm32_omm *omm = dev_get_drvdata(dev); >>>>>> + struct reset_control *reset; >>>>>> + int ret; >>>>>> + u8 i; >>>>>> + >>>>>> + for (i = 0; i < omm->nb_child; i++) { >>>>>> + ret = clk_prepare_enable(omm->child[i].clk); >>>>>> + if (ret) { >>>>>> + dev_err(dev, "Can not enable clock\n"); >>>>>> + return ret; >>>>>> + } >>>>>> + >>>>>> + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); >>>>>> + if (IS_ERR(reset)) { >>>>>> + dev_err(dev, "Can't get child reset\n"); >>>>> >>>>> Why do you get reset of child? Parent is not suppposed to poke there. >>>>> You might not have the reset there in the first place and it would not >>>>> be an error. >>>> >>>> By ressetting child (OSPI), we ensure they are disabled and in a known state. >>>> See the comment below. >>>> >>>>> >>>>> >>>>>> + return PTR_ERR(reset); >>>>>> + }; >>>>>> + >>>>>> + /* reset OSPI to ensure CR_EN bit is set to 0 */ >>>>>> + reset_control_assert(reset); >>>>>> + udelay(2); >>>>>> + reset_control_deassert(reset); >>>>> >>>>> No, the child should handle this, not parent. >>>> >>>> Octo Memory Manager can only be configured if both child are disabled. >>>> That's why here, parent handles this. >>> >>> So if device by any chance started and is doing some useful work, then >>> you cancel that work and reset it? >> >> stm32_omm_configure() is only called if we get access granted on both children. >> That means we are authorized to use these devices, so we can reset them. >> >>> >>> And what if child does not have reset line? Your binding allows that, so >>> how is it supposed to work then? >> >> Ah yes, you are right, the OSPI bindings need to be updated >> by requiring reset lines and the driver spi-stm32-ospi.c as well. >> I will send a fix for that. >> >> Thanks for pointing this. >> >>> >>> This also leads me to questions about bindings - if you need to assert >>> some reset, doesn't it mean that these resets are also coming through >>> this device so they are part of this device node? >> >> As we are able to retrieve children's reset from their respective node, >> if you don't mind, OMM bindings can be kept as it's currently. > > But that is what the entire discussion is about - I do mind. I said it > already - you are not supposed to poke into child's node. > > If you need to toggle child's resources, then I claim these are your > resources as well. Hi Krzysztof Ok i will update both OMM driver and bindings accordingly. > >> >> And another information, on some MP2 SoCs family, there is only one >> OSPI instance. So for these SoCs, there is no Octo Memory Manager. >> >>> >>>> >>>>> >>>>>> + >>>>>> + reset_control_put(reset); >>>>>> + clk_disable_unprepare(omm->child[i].clk); >>>>>> + } >>>>>> + >>>>>> + return 0; >>>>>> +} >>>>>> + >>>>>> +static int stm32_omm_probe(struct platform_device *pdev) >>>>>> +{ >>>>>> + struct platform_device *vdev; >>>>>> + struct device *dev = &pdev->dev; >>>>>> + struct stm32_omm *omm; >>>>>> + struct clk *clk; >>>>>> + int ret; >>>>>> + u8 child_access_granted = 0; >>>>> >>>>> Keep inits/assignments together >>>> >>>> ok >>>> >>>>> >>>>>> + u8 i, j; >>>>>> + bool child_access[OMM_CHILD_NB]; >>>>>> + >>>>>> + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); >>>>>> + if (!omm) >>>>>> + return -ENOMEM; >>>>>> + >>>>>> + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); >>>>>> + if (IS_ERR(omm->io_base)) >>>>>> + return PTR_ERR(omm->io_base); >>>>>> + >>>>>> + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); >>>>>> + if (IS_ERR(omm->mm_res)) >>>>>> + return PTR_ERR(omm->mm_res); >>>>>> + >>>>>> + /* check child's access */ >>>>>> + for_each_child_of_node_scoped(dev->of_node, child) { >>>>>> + if (omm->nb_child >= OMM_CHILD_NB) { >>>>>> + dev_err(dev, "Bad DT, found too much children\n"); >>>>>> + ret = -E2BIG; >>>>>> + goto err_clk_release; >>>>>> + } >>>>>> + >>>>>> + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { >>>>>> + ret = -EINVAL; >>>>>> + goto err_clk_release; >>>>>> + } >>>>>> + >>>>>> + ret = stm32_omm_check_access(dev, child); >>>>>> + if (ret < 0 && ret != -EACCES) >>>>>> + goto err_clk_release; >>>>>> + >>>>>> + child_access[omm->nb_child] = false; >>>>>> + if (!ret) { >>>>>> + child_access_granted++; >>>>>> + child_access[omm->nb_child] = true; >>>>>> + } >>>>>> + >>>>>> + omm->child[omm->nb_child].node = child; >>>>>> + >>>>>> + clk = of_clk_get(child, 0); >>>>> >>>>> Why are you taking children clock? And why with this API, not clk_get? >>>> >>>> I need children's clock to reset them. >>> >>> >>> The device driver should reset its device. It is not a discoverable bus, >>> that would explain power sequencing from the parent. >>> >>>> Why of_clk_get() usage is a problem here ? i can't get your point ? >>> >>> Because it is not the API which device drivers should use. You should >>> use clk_get or devm_clk_get. >> >> >> ok, i will update this part using clk_get(). >> >>> >>> >>>> >>>>> This looks like mixing clock provider in the clock consumer. >>>>> >>>>>> + if (IS_ERR(clk)) { >>>>>> + dev_err(dev, "Can't get child clock\n"); >>>>> >>>>> Syntax is always return dev_err_probe (or ret = dev_err_probe). >>>> >>>> ok >>>> >>>>> >>>>>> + ret = PTR_ERR(clk); >>>>>> + goto err_clk_release; >>>>>> + }; >>>>>> + >>>>>> + omm->child[omm->nb_child].clk = clk; >>>>>> + omm->nb_child++; >>>>>> + } >>>>>> + >>>>>> + if (omm->nb_child != OMM_CHILD_NB) { >>>>>> + ret = -EINVAL; >>>>>> + goto err_clk_release; >>>>>> + } >>>>>> + >>>>>> + platform_set_drvdata(pdev, omm); >>>>>> + >>>>>> + pm_runtime_enable(dev); >>>>>> + >>>>>> + /* check if OMM's resource access is granted */ >>>>>> + ret = stm32_omm_check_access(dev, dev->of_node); >>>>>> + if (ret < 0 && ret != -EACCES) >>>>>> + goto err_clk_release; >>>>>> + >>>>>> + if (!ret && child_access_granted == OMM_CHILD_NB) { >>>>>> + /* Ensure both OSPI instance are disabled before configuring OMM */ >>>>>> + ret = stm32_omm_disable_child(dev); >>>>>> + if (ret) >>>>>> + goto err_clk_release; >>>>>> + >>>>>> + ret = stm32_omm_configure(dev); >>>>>> + if (ret) >>>>>> + goto err_clk_release; >>>>>> + } else { >>>>>> + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); >>>>>> + /* >>>>>> + * AMCR can't be set, so check if current value is coherent >>>>>> + * with memory-map areas defined in DT >>>>>> + */ >>>>>> + ret = stm32_omm_set_amcr(dev, false); >>>>>> + if (ret) >>>>>> + goto err_clk_release; >>>>>> + } >>>>>> + >>>>>> + /* for each child, if resource access is granted and status "okay", probe it */ >>>>>> + for (i = 0; i < omm->nb_child; i++) { >>>>>> + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) >>>>> >>>>> If you have a device available, why do you create one more platform device? >>>>> >>>>>> + continue; >>>>>> + >>>>>> + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); >>>>> >>>>> Why you cannot just populate the children? >>>> >>>> I can't use of_platform_populate(), by default it will populate all OMM's child. >>>> Whereas here, we want to probe only the OMM's child which match our criteria. >>> >>> >>> Why wouldn't you populate everyone? The task of bus driver is not to >>> filter out DT. If you got such DT - with all device nodes - you are >>> expected to populate all of them. Otherwise, if you do not want all of >>> them, it is expected that firmware or bootloader will give you DT >>> without these nodes. >> >> We don't want to populate every child by default because we can get >> cases where one child is shared between Cortex A and Cortex M. > > But in such case DTB would not have that child enabled. > >> That's why we must check if access is granted which ensure that >> firewall semaphore is available (RIFSC semaphore in our case). > > If you do not have access, means child is assigned to other processor, > right? In that case that child would not have been enabled in your DTB. > > Fix your DTB instead of creating another layer of handling children > inside drivers. In fact, initially, we wanted to avoid to trigger Illegal Access in case user didn't use correct DT, that's why, here, double checks have been implemented. But Ok, i will clean this part and simply populate children. Thanks Patrice. > > > Best regards, > Krzysztof
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index c82d8d8a16ea..3a0703fbfee7 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -225,6 +225,23 @@ config STM32_FMC2_EBI devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on SOCs containing the FMC2 External Bus Interface. +config STM32_OMM + tristate "STM32 Octo Memory Manager" + depends on SPI_STM32_OSPI || COMPILE_TEST + help + This driver manages the muxing between the 2 OSPI busses and + the 2 output ports. There are 4 possible muxing configurations: + - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 + output is on port 2 + - OSPI1 and OSPI2 are multiplexed over the same output port 1 + - swapped mode (no multiplexing), OSPI1 output is on port 2, + OSPI2 output is on port 1 + - OSPI1 and OSPI2 are multiplexed over the same output port 2 + It also manages : + - the split of the memory area shared between the 2 OSPI instances. + - chip select selection override. + - the time between 2 transactions in multiplexed mode. + source "drivers/memory/samsung/Kconfig" source "drivers/memory/tegra/Kconfig" diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index d2e6ca9abbe0..c1959661bf63 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o obj-$(CONFIG_PL353_SMC) += pl353-smc.o obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o +obj-$(CONFIG_STM32_OMM) += stm32_omm.o obj-$(CONFIG_SAMSUNG_MC) += samsung/ obj-$(CONFIG_TEGRA_MC) += tegra/ diff --git a/drivers/memory/stm32_omm.c b/drivers/memory/stm32_omm.c new file mode 100644 index 000000000000..8f7f475769e7 --- /dev/null +++ b/drivers/memory/stm32_omm.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroelectronics. + */ + +#include <linux/bitfield.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/mfd/syscon.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +#define OMM_CR 0 +#define CR_MUXEN BIT(0) +#define CR_MUXENMODE_MASK GENMASK(1, 0) +#define CR_CSSEL_OVR_EN BIT(4) +#define CR_CSSEL_OVR_MASK GENMASK(6, 5) +#define CR_REQ2ACK_MASK GENMASK(23, 16) + +#define OMM_CHILD_NB 2 + +struct ospi_child { + struct device *dev; + struct device_node *node; + struct clk *clk; +}; + +struct stm32_omm { + struct ospi_child child[OMM_CHILD_NB]; + struct resource *mm_res; + struct clk *clk; + void __iomem *io_base; + u32 cr; + u8 nb_child; + bool restore_omm; +}; + +static int stm32_omm_set_amcr(struct device *dev, bool set) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + struct regmap *syscfg_regmap; + struct device_node *node; + struct resource res, res1; + resource_size_t mm_ospi2_size = 0; + static const char * const mm_name[] = { "ospi1", "ospi2" }; + u32 amcr_base, amcr_mask; + int ret, idx; + unsigned int i, amcr, read_amcr; + + for (i = 0; i < omm->nb_child; i++) { + idx = of_property_match_string(dev->of_node, + "memory-region-names", + mm_name[i]); + if (idx < 0) + continue; + + /* res1 only used on second loop iteration */ + res1.start = res.start; + res1.end = res.end; + + node = of_parse_phandle(dev->of_node, "memory-region", idx); + if (!node) + continue; + + ret = of_address_to_resource(node, 0, &res); + if (ret) { + dev_err(dev, "unable to resolve memory region\n"); + return ret; + } + + /* check that memory region fits inside OMM memory map area */ + if (!resource_contains(omm->mm_res, &res)) { + dev_err(dev, "%s doesn't fit inside OMM memory map area\n", + mm_name[i]); + dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res); + + return -EFAULT; + } + + if (i == 1) { + mm_ospi2_size = resource_size(&res); + + /* check that OMM memory region 1 doesn't overlap memory region 2 */ + if (resource_overlaps(&res, &res1)) { + dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", + mm_name[0], mm_name[1]); + dev_err(dev, "%pR overlaps %pR\n", &res1, &res); + + return -EFAULT; + } + } + } + + syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr"); + if (IS_ERR(syscfg_regmap)) { + dev_err(dev, "Failed to get st,syscfg-amcr property\n"); + return PTR_ERR(syscfg_regmap); + } + + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1, + &amcr_base); + if (ret) + return ret; + + ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2, + &amcr_mask); + if (ret) + return ret; + + amcr = mm_ospi2_size / SZ_64M; + + if (set) + regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr); + + /* read AMCR and check coherency with memory-map areas defined in DT */ + regmap_read(syscfg_regmap, amcr_base, &read_amcr); + read_amcr = read_amcr >> (ffs(amcr_mask) - 1); + + if (amcr != read_amcr) { + dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); + ret = -EINVAL; + } + + return ret; +} + +static int stm32_omm_enable_child_clock(struct device *dev, bool enable) +{ + /* As there is only 2 children, remember first child in case of error */ + struct clk *first_child_clk = NULL; + struct stm32_omm *omm = dev_get_drvdata(dev); + u8 i; + int ret; + + for (i = 0; i < omm->nb_child; i++) { + if (enable) { + ret = clk_prepare_enable(omm->child[i].clk); + if (ret) { + if (first_child_clk) + clk_disable_unprepare(first_child_clk); + + dev_err(dev, "Can not enable clock\n"); + return ret; + } + } else { + clk_disable_unprepare(omm->child[i].clk); + } + + first_child_clk = omm->child[i].clk; + } + + return 0; +} + +static int stm32_omm_configure(struct device *dev) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + struct reset_control *rstc; + unsigned long clk_rate, clk_rate_max = 0; + int ret; + u8 i; + u32 mux = 0; + u32 cssel_ovr = 0; + u32 req2ack = 0; + + omm->clk = devm_clk_get(dev, NULL); + if (IS_ERR(omm->clk)) { + dev_err(dev, "Failed to get OMM clock (%ld)\n", + PTR_ERR(omm->clk)); + + return PTR_ERR(omm->clk); + } + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + /* parse children's clock */ + for (i = 0; i < omm->nb_child; i++) { + clk_rate = clk_get_rate(omm->child[i].clk); + if (!clk_rate) { + dev_err(dev, "Invalid clock rate\n"); + pm_runtime_disable(dev); + goto err_clk_disable; + } + + if (clk_rate > clk_rate_max) + clk_rate_max = clk_rate; + } + + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(rstc)) { + ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); + pm_runtime_disable(dev); + goto err_clk_disable; + } + + reset_control_assert(rstc); + udelay(2); + reset_control_deassert(rstc); + + omm->cr = readl_relaxed(omm->io_base + OMM_CR); + /* optional */ + ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux); + if (!ret) { + if (mux & CR_MUXEN) { + ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", + &req2ack); + if (!ret && !req2ack) { + req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; + + if (req2ack > 256) + req2ack = 256; + } + + req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); + + omm->cr &= ~CR_REQ2ACK_MASK; + omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack); + + /* + * If the mux is enabled, the 2 OSPI clocks have to be + * always enabled + */ + ret = stm32_omm_enable_child_clock(dev, true); + if (ret) { + pm_runtime_disable(dev); + goto err_clk_disable; + } + } + + omm->cr &= ~CR_MUXENMODE_MASK; + omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux); + } + + /* optional */ + ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr); + if (!ret) { + omm->cr &= ~CR_CSSEL_OVR_MASK; + omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); + omm->cr |= CR_CSSEL_OVR_EN; + } + + omm->restore_omm = true; + writel_relaxed(omm->cr, omm->io_base + OMM_CR); + + ret = stm32_omm_set_amcr(dev, true); + +err_clk_disable: + pm_runtime_put_sync_suspend(dev); + + return ret; +} + +static int stm32_omm_check_access(struct device *dev, struct device_node *np) +{ + struct stm32_firewall firewall; + int ret; + + ret = stm32_firewall_get_firewall(np, &firewall, 1); + if (ret) + return ret; + + return stm32_firewall_grant_access(&firewall); +} + +static int stm32_omm_disable_child(struct device *dev) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + struct reset_control *reset; + int ret; + u8 i; + + for (i = 0; i < omm->nb_child; i++) { + ret = clk_prepare_enable(omm->child[i].clk); + if (ret) { + dev_err(dev, "Can not enable clock\n"); + return ret; + } + + reset = of_reset_control_get_exclusive(omm->child[i].node, 0); + if (IS_ERR(reset)) { + dev_err(dev, "Can't get child reset\n"); + return PTR_ERR(reset); + }; + + /* reset OSPI to ensure CR_EN bit is set to 0 */ + reset_control_assert(reset); + udelay(2); + reset_control_deassert(reset); + + reset_control_put(reset); + clk_disable_unprepare(omm->child[i].clk); + } + + return 0; +} + +static int stm32_omm_probe(struct platform_device *pdev) +{ + struct platform_device *vdev; + struct device *dev = &pdev->dev; + struct stm32_omm *omm; + struct clk *clk; + int ret; + u8 child_access_granted = 0; + u8 i, j; + bool child_access[OMM_CHILD_NB]; + + omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); + if (!omm) + return -ENOMEM; + + omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); + if (IS_ERR(omm->io_base)) + return PTR_ERR(omm->io_base); + + omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); + if (IS_ERR(omm->mm_res)) + return PTR_ERR(omm->mm_res); + + /* check child's access */ + for_each_child_of_node_scoped(dev->of_node, child) { + if (omm->nb_child >= OMM_CHILD_NB) { + dev_err(dev, "Bad DT, found too much children\n"); + ret = -E2BIG; + goto err_clk_release; + } + + if (!of_device_is_compatible(child, "st,stm32mp25-ospi")) { + ret = -EINVAL; + goto err_clk_release; + } + + ret = stm32_omm_check_access(dev, child); + if (ret < 0 && ret != -EACCES) + goto err_clk_release; + + child_access[omm->nb_child] = false; + if (!ret) { + child_access_granted++; + child_access[omm->nb_child] = true; + } + + omm->child[omm->nb_child].node = child; + + clk = of_clk_get(child, 0); + if (IS_ERR(clk)) { + dev_err(dev, "Can't get child clock\n"); + ret = PTR_ERR(clk); + goto err_clk_release; + }; + + omm->child[omm->nb_child].clk = clk; + omm->nb_child++; + } + + if (omm->nb_child != OMM_CHILD_NB) { + ret = -EINVAL; + goto err_clk_release; + } + + platform_set_drvdata(pdev, omm); + + pm_runtime_enable(dev); + + /* check if OMM's resource access is granted */ + ret = stm32_omm_check_access(dev, dev->of_node); + if (ret < 0 && ret != -EACCES) + goto err_clk_release; + + if (!ret && child_access_granted == OMM_CHILD_NB) { + /* Ensure both OSPI instance are disabled before configuring OMM */ + ret = stm32_omm_disable_child(dev); + if (ret) + goto err_clk_release; + + ret = stm32_omm_configure(dev); + if (ret) + goto err_clk_release; + } else { + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); + /* + * AMCR can't be set, so check if current value is coherent + * with memory-map areas defined in DT + */ + ret = stm32_omm_set_amcr(dev, false); + if (ret) + goto err_clk_release; + } + + /* for each child, if resource access is granted and status "okay", probe it */ + for (i = 0; i < omm->nb_child; i++) { + if (!child_access[i] || !of_device_is_available(omm->child[i].node)) + continue; + + vdev = of_platform_device_create(omm->child[i].node, NULL, NULL); + if (!vdev) { + dev_err(dev, "Failed to create Octo Memory Manager child\n"); + for (j = i; j > 0; --j) { + if (omm->child[j].dev) + of_platform_device_destroy(omm->child[j].dev, NULL); + } + + ret = -EINVAL; + goto err_clk_release; + } + omm->child[i].dev = &vdev->dev; + } + +err_clk_release: + for (i = 0; i < omm->nb_child; i++) + clk_put(omm->child[i].clk); + + return ret; +} + +static void stm32_omm_remove(struct platform_device *pdev) +{ + struct stm32_omm *omm = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < omm->nb_child; i++) + if (omm->child[i].dev) + of_platform_device_destroy(omm->child[i].dev, NULL); + + if (omm->cr & CR_MUXEN) + stm32_omm_enable_child_clock(&pdev->dev, false); + + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id stm32_omm_of_match[] = { + { .compatible = "st,stm32mp25-omm", }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_omm_of_match); + +static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + + clk_disable_unprepare(omm->clk); + + return 0; +} + +static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + + return clk_prepare_enable(omm->clk); +} + +static int __maybe_unused stm32_omm_suspend(struct device *dev) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + + if (omm->restore_omm && omm->cr & CR_MUXEN) + stm32_omm_enable_child_clock(dev, false); + + return pinctrl_pm_select_sleep_state(dev); +} + +static int __maybe_unused stm32_omm_resume(struct device *dev) +{ + struct stm32_omm *omm = dev_get_drvdata(dev); + int ret; + + pinctrl_pm_select_default_state(dev); + + if (!omm->restore_omm) + return 0; + + /* Ensure both OSPI instance are disabled before configuring OMM */ + ret = stm32_omm_disable_child(dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + writel_relaxed(omm->cr, omm->io_base + OMM_CR); + ret = stm32_omm_set_amcr(dev, true); + pm_runtime_put_sync_suspend(dev); + if (ret) + return ret; + + if (omm->cr & CR_MUXEN) + ret = stm32_omm_enable_child_clock(dev, true); + + return ret; +} + +static const struct dev_pm_ops stm32_omm_pm_ops = { + SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend, + stm32_omm_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume) +}; + +static struct platform_driver stm32_omm_driver = { + .probe = stm32_omm_probe, + .remove = stm32_omm_remove, + .driver = { + .name = "stm32-omm", + .of_match_table = stm32_omm_of_match, + .pm = &stm32_omm_pm_ops, + }, +}; +module_platform_driver(stm32_omm_driver); + +MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver"); +MODULE_LICENSE("GPL");