| Message ID | 20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: qcom: x1e80100: Add crypto engine | expand |
On Fri, Feb 21, 2025 at 03:07:03PM +0200, Abel Vesa wrote: > On X Elite, there is a crypto engine IP block similar to ones found on > SM8x50 platforms. > > Describe the crypto engine and its BAM. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > The dt-binding schema update for the x1e80100 compatible is here > (already picked up): > > https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/ > --- > Changes in v2: > - Added EE and channels numbers in BAM node, like Stephan suggested. > - Added v1.7.4 compatible as well. > - Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 9d38436763432892ceef95daf0335d4cf446357c..71d5f5eed4511030a51fb12e453f603d294080cc 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3708,6 +3708,38 @@ pcie4_phy: phy@1c0e000 { > status = "disabled"; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0 0x01dc4000 0 0x28000>; > + > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + > + #dma-cells = <1>; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; > + > + qcom,ee = <0>; > + qcom,num-ees = <7>; > + num-channels = <30>; Hm, the hardware registers report the same as SM8550 on my X1E CRD: qcom,num-ees = <4>; num-channels = <20>; [ 17.679161] bam-dma-engine 1dc4000.dma-controller: bam_init() ees 4 [ 17.679163] bam-dma-engine 1dc4000.dma-controller: bam_init() num-channels 20 [ 17.679164] ------------[ cut here ]------------ [ 17.679165] bam-dma-engine 1dc4000.dma-controller: DT specifies num-channels = <30>, but hardware reports 20. Please fix the device tree! [ 17.679175] WARNING: CPU: 5 PID: 121 at drivers/dma/qcom/bam_dma.c:498 bam_init+0x10c/0x150 [bam_dma] (You don't have this warning yet, it's part of an upcoming bam_dma patch series from me that will start validating the num-channels given in the device tree.) > + qcom,controlled-remotely; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; > + reg = <0 0x01dfa000 0 0x6000>; > + > + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "memory"; > + > + dmas = <&cryptobam 4>, <&cryptobam 5>; > + dma-names = "rx", "tx"; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; iommus = <&apps_smmu 0x480 0x1> seems to work fine for me, can you try again? Not sure if this is related, but make sure to apply https://lore.kernel.org/linux-arm-msm/20250208223112.142567-1-caleb.connolly@linaro.org/ since that can easily cause crashes for bam_dma. I added this diff for testing and it's working fine so far: diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index afb8bd3b6a94..bac3d6a38055 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3732,8 +3732,7 @@ cryptobam: dma-controller@1dc4000 { #dma-cells = <1>; - iommus = <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; + iommus = <&apps_smmu 0x480 0x1>; qcom,ee = <0>; qcom,num-ees = <4>; @@ -3752,8 +3751,7 @@ crypto: crypto@1dfa000 { dmas = <&cryptobam 4>, <&cryptobam 5>; dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; + iommus = <&apps_smmu 0x480 0x1>; }; tcsr_mutex: hwlock@1f40000 { Thanks, Stephan
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9d38436763432892ceef95daf0335d4cf446357c..71d5f5eed4511030a51fb12e453f603d294080cc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3708,6 +3708,38 @@ pcie4_phy: phy@1c0e000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <7>; + num-channels = <30>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>;
On X Elite, there is a crypto engine IP block similar to ones found on SM8x50 platforms. Describe the crypto engine and its BAM. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- The dt-binding schema update for the x1e80100 compatible is here (already picked up): https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/ --- Changes in v2: - Added EE and channels numbers in BAM node, like Stephan suggested. - Added v1.7.4 compatible as well. - Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) --- base-commit: d4b0fd87ff0d4338b259dc79b2b3c6f7e70e8afa change-id: 20250213-x1e80100-crypto-18c7d14cd459 Best regards,