| Message ID | 20250226151458.3871867-2-niklas.neronin@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] usb: xhci: use correct TR Dequeue pointer mask | expand |
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 965bffce301e..d4ec1e707107 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -1464,7 +1464,7 @@ static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, stream_ctx->reserved[1] = 0; } } else { - deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; + deq = le64_to_cpu(ep_ctx->deq) & SCTX_DEQ_MASK; } xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
The Endpoint Context Field at Offset 0x08 is defined as follows: - Bit 0: Dequeue Cycle State (DCS) - Bits 3:1: RsvdZ (Reserved and Zero) - Bits 63:4: TR Dequeue Pointer When reading the TR Dequeue Pointer for an Endpoint without Streams, the inverted Dequeue Cycle State mask ('~EP_CTX_CYCLE_MASK') is used, which include the Reserved bits. Although bits 3:1 are typically zero, using the incorrect mask could potentially cause issues. Swap mask 'EP_CTX_CYCLE_MASK' for 'SCTX_DEQ_MASK'. i.e. ~(1 << 0) for (~0xfL). Signed-off-by: Niklas Neronin <niklas.neronin@linux.intel.com> --- drivers/usb/host/xhci-ring.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)